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5 Commits

Author SHA1 Message Date
Binbin Zhou
4f149dd478 clk: clk-loongson2: Add Loongson-2K2000 clock support 
The Loongson-2K2000 and Loongson-2K1000 clock is similar, we add its
support by different configurations.

Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Link: https://lore.kernel.org/r/8b0b5851783acf8ebe13b50391d15b58cc181613.1712731524.git.zhoubinbin@loongson.cn
Acked-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-04-11 00:30:13 -07:00
Binbin Zhou
85d4daa595 clk: clk-loongson2: Add Loongson-2K0500 clock support 
The Loongson-2K0500 and Loongson-2K1000 clock is similar, we add its
support by different configurations.

Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Link: https://lore.kernel.org/r/f767a1783dc590fcd31ff7d4459df2cf80196de1.1712731524.git.zhoubinbin@loongson.cn
Acked-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-04-11 00:30:08 -07:00
Binbin Zhou
9796ec0bd0 clk: clk-loongson2: Refactor driver for adding new platforms 
The driver only supported loongson-2K1000 at first, but the clock
structure of loongson-2K0500 and loongson-2K2000 are actually similar,
and I tried to refactor the whole driver to adjust to the addition of
the new platform.

Briefly, I have divided all clocks into three categories according to
their properties and their parent clocks: Independent PLLs, clocks based
on frequency scales, and clock dividers.

Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Link: https://lore.kernel.org/r/fb020d1ca19e6f4cdcc95c87b2748869ca76b8ec.1712731524.git.zhoubinbin@loongson.cn
Acked-by: Huacai Chen <chenhuacai@loongson.cn>
[sboyd@kernel.org: Drop clk.h include]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-04-11 00:30:00 -07:00
Binbin Zhou
2a809ddca0 clk: clk-loongson2: Zero init clk_init_data 
As clk_core_populate_parent_map() checks clk_init_data.num_parents
first, and checks clk_init_data.parent_names[] before
clk_init_data.parent_data[] and clk_init_data.parent_hws[].

Therefore the clk_init_data structure needs to be explicitly initialised
to prevent an unexpected crash if clk_init_data.parent_names[] is a
random value.

 CPU 0 Unable to handle kernel paging request at virtual address 0000000000000dc0, era == 9000000002986290, ra == 900000000298624c
 Oops[#1]:
 CPU: 0 PID: 1 Comm: swapper/0 Not tainted 6.4.0-rc2+ #4582
 pc 9000000002986290 ra 900000000298624c tp 9000000100094000 sp 9000000100097a60
 a0 9000000104541e00 a1 0000000000000000 a2 0000000000000dc0 a3 0000000000000001
 a4 90000001000979f0 a5 90000001800977d7 a6 0000000000000000 a7 900000000362a000
 t0 90000000034f3548 t1 6f8c2a9cb5ab5f64 t2 0000000000011340 t3 90000000031cf5b0
 t4 0000000000000dc0 t5 0000000000000004 t6 0000000000011300 t7 9000000104541e40
 t8 000000000005a4f8 u0 9000000104541e00 s9 9000000104541e00 s0 9000000104bc4700
 s1 9000000104541da8 s2 0000000000000001 s3 900000000356f9d8 s4 ffffffffffffffff
 s5 0000000000000000 s6 0000000000000dc0 s7 90000000030d0a88 s8 0000000000000000
    ra: 900000000298624c __clk_register+0x228/0x84c
   ERA: 9000000002986290 __clk_register+0x26c/0x84c
  CRMD: 000000b0 (PLV0 -IE -DA +PG DACF=CC DACM=CC -WE)
  PRMD: 00000004 (PPLV0 +PIE -PWE)
  EUEN: 00000000 (-FPE -SXE -ASXE -BTE)
  ECFG: 00071c1c (LIE=2-4,10-12 VS=7)
 ESTAT: 00010000 [PIL] (IS= ECode=1 EsubCode=0)
  BADV: 0000000000000dc0
  PRID: 0014a000 (Loongson-64bit, )
 Modules linked in:
 Process swapper/0 (pid: 1, threadinfo=(____ptrval____), task=(____ptrval____))
 Stack : 90000000031c1810 90000000030d0a88 900000000325bac0 90000000034f3548
         90000001002ab410 9000000104541e00 0000000000000dc0 9000000003150098
         90000000031c1810 90000000031a0460 900000000362a000 90000001002ab410
         900000000362a000 9000000104541da8 9000000104541de8 90000001002ab410
         900000000362a000 9000000002986a68 90000000034f3ed8 90000000030d0aa8
         9000000104541da8 900000000298d3b8 90000000031c1810 0000000000000000
         90000000034f3ed8 90000000030d0aa8 0000000000000dc0 90000000030d0a88
         90000001002ab410 900000000298d401 0000000000000000 6f8c2a9cb5ab5f64
         90000000034f4000 90000000030d0a88 9000000003a48a58 90000001002ab410
         9000000104bd81a8 900000000298d484 9000000100020260 0000000000000000
         ...
 Call Trace:
 [<9000000002986290>] __clk_register+0x26c/0x84c
 [<9000000002986a68>] devm_clk_hw_register+0x5c/0xe0
 [<900000000298d3b8>] loongson2_clk_register.constprop.0+0xdc/0x10c
 [<900000000298d484>] loongson2_clk_probe+0x9c/0x4ac
 [<9000000002a4eba4>] platform_probe+0x68/0xc8
 [<9000000002a4bf80>] really_probe+0xbc/0x2f0
 [<9000000002a4c23c>] __driver_probe_device+0x88/0x128
 [<9000000002a4c318>] driver_probe_device+0x3c/0x11c
 [<9000000002a4c5dc>] __driver_attach+0x98/0x18c
 [<9000000002a49ca0>] bus_for_each_dev+0x80/0xe0
 [<9000000002a4b0dc>] bus_add_driver+0xfc/0x1ec
 [<9000000002a4d4a8>] driver_register+0x68/0x134
 [<90000000020f0110>] do_one_initcall+0x50/0x188
 [<9000000003150f00>] kernel_init_freeable+0x224/0x294
 [<90000000030240fc>] kernel_init+0x20/0x110
 [<90000000020f1568>] ret_from_kernel_thread+0xc/0xa4

Fixes: acc0ccffec50 ("clk: clk-loongson2: add clock controller driver support")
Cc: stable@vger.kernel.org
Cc: Yinbo Zhu <zhuyinbo@loongson.cn>
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Link: https://lore.kernel.org/r/20230524014924.2869051-1-zhoubinbin@loongson.cn
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-06-12 18:30:46 -07:00
Yinbo Zhu
acc0ccffec clk: clk-loongson2: add clock controller driver support 
This driver provides support for clock controller on Loongson-2 SoC,
the Loongson-2 SoC uses a 100MHz clock as the PLL reference clock,
there are five independent PLLs inside, each of which PLL can
provide up to three sets of frequency dependent clock outputs.

Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Link: https://lore.kernel.org/r/20230323025229.2971-2-zhuyinbo@loongson.cn
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-27 12:15:26 -07:00