# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause %YAML 1.2 --- $id: http://devicetree.org/schemas/display/msm/dpu-msm8998.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Display DPU dt properties for MSM8998 target maintainers: - AngeloGioacchino Del Regno description: | Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree bindings of MDSS and DPU are mentioned for MSM8998 target. $ref: /schemas/display/msm/mdss-common.yaml# properties: compatible: items: - const: qcom,msm8998-mdss clocks: items: - description: Display AHB clock - description: Display AXI clock - description: Display core clock clock-names: items: - const: iface - const: bus - const: core iommus: maxItems: 1 patternProperties: "^display-controller@[0-9a-f]+$": type: object $ref: /schemas/display/msm/dpu-common.yaml# description: Node containing the properties of DPU. unevaluatedProperties: false properties: compatible: items: - const: qcom,msm8998-dpu reg: items: - description: Address offset and size for mdp register set - description: Address offset and size for regdma register set - description: Address offset and size for vbif register set - description: Address offset and size for non-realtime vbif register set reg-names: items: - const: mdp - const: regdma - const: vbif - const: vbif_nrt clocks: items: - description: Display ahb clock - description: Display axi clock - description: Display mem-noc clock - description: Display core clock - description: Display vsync clock clock-names: items: - const: iface - const: bus - const: mnoc - const: core - const: vsync unevaluatedProperties: false examples: - | #include #include #include mdss: display-subsystem@c900000 { compatible = "qcom,msm8998-mdss"; reg = <0x0c900000 0x1000>; reg-names = "mdss"; clocks = <&mmcc MDSS_AHB_CLK>, <&mmcc MDSS_AXI_CLK>, <&mmcc MDSS_MDP_CLK>; clock-names = "iface", "bus", "core"; #address-cells = <1>; #interrupt-cells = <1>; #size-cells = <1>; interrupts = ; interrupt-controller; iommus = <&mmss_smmu 0>; power-domains = <&mmcc MDSS_GDSC>; ranges; display-controller@c901000 { compatible = "qcom,msm8998-dpu"; reg = <0x0c901000 0x8f000>, <0x0c9a8e00 0xf0>, <0x0c9b0000 0x2008>, <0x0c9b8000 0x1040>; reg-names = "mdp", "regdma", "vbif", "vbif_nrt"; clocks = <&mmcc MDSS_AHB_CLK>, <&mmcc MDSS_AXI_CLK>, <&mmcc MNOC_AHB_CLK>, <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_VSYNC_CLK>; clock-names = "iface", "bus", "mnoc", "core", "vsync"; interrupt-parent = <&mdss>; interrupts = <0>; operating-points-v2 = <&mdp_opp_table>; power-domains = <&rpmpd MSM8998_VDDMX>; ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; dpu_intf1_out: endpoint { remote-endpoint = <&dsi0_in>; }; }; port@1 { reg = <1>; dpu_intf2_out: endpoint { remote-endpoint = <&dsi1_in>; }; }; }; }; }; ...