633743ed18
The function ast_crtc_dpms() is left over from when the ast driver did not implement atomic modesetting. But DPMS is not supported by atomic modesetting and the helper is only called to enable or disable the CRTC sync pulses. Inline the function into its callers. To disable the CRTC, ast sets (AST_DPMS_VSYNC_OFF | AST_DPMS_HSYNC_OFF) in VGACRB6. Replace the constants with the correct register constants for VGACRB6. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240627153638.8765-8-tzimmermann@suse.de
104 lines
2.5 KiB
C
104 lines
2.5 KiB
C
/* SPDX-License-Identifier: MIT */
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#ifndef __AST_REG_H__
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#define __AST_REG_H__
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#include <linux/bits.h>
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/*
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* Modesetting
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*/
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#define AST_IO_MM_OFFSET (0x380)
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#define AST_IO_MM_LENGTH (128)
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#define AST_IO_VGAARI_W (0x40)
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#define AST_IO_VGAMR_W (0x42)
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#define AST_IO_VGAMR_R (0x4c)
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#define AST_IO_VGAMR_IOSEL BIT(0)
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#define AST_IO_VGAER (0x43)
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#define AST_IO_VGAER_VGA_ENABLE BIT(0)
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#define AST_IO_VGASRI (0x44)
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#define AST_IO_VGASR1_SD BIT(5)
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#define AST_IO_VGADRR (0x47)
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#define AST_IO_VGADWR (0x48)
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#define AST_IO_VGAPDR (0x49)
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#define AST_IO_VGAGRI (0x4E)
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#define AST_IO_VGACRI (0x54)
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#define AST_IO_VGACR80_PASSWORD (0xa8)
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#define AST_IO_VGACRA1_VGAIO_DISABLED BIT(1)
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#define AST_IO_VGACRA1_MMIO_ENABLED BIT(2)
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#define AST_IO_VGACRB6_HSYNC_OFF BIT(0)
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#define AST_IO_VGACRB6_VSYNC_OFF BIT(1)
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#define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
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#define AST_IO_VGACRCB_HWC_ENABLED BIT(1)
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#define AST_IO_VGAIR1_R (0x5A)
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#define AST_IO_VGAIR1_VREFRESH BIT(3)
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/*
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* Display Transmitter Type
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*/
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#define TX_TYPE_MASK GENMASK(3, 1)
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#define NO_TX (0 << 1)
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#define ITE66121_VBIOS_TX (1 << 1)
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#define SI164_VBIOS_TX (2 << 1)
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#define CH7003_VBIOS_TX (3 << 1)
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#define DP501_VBIOS_TX (4 << 1)
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#define ANX9807_VBIOS_TX (5 << 1)
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#define TX_FW_EMBEDDED_FW_TX (6 << 1)
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#define ASTDP_DPMCU_TX (7 << 1)
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#define AST_VRAM_INIT_STATUS_MASK GENMASK(7, 6)
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//#define AST_VRAM_INIT_BY_BMC BIT(7)
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//#define AST_VRAM_INIT_READY BIT(6)
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/*
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* AST DisplayPort
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*/
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/* Define for Soc scratched reg used on ASTDP */
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#define AST_DP_PHY_SLEEP BIT(4)
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#define AST_DP_VIDEO_ENABLE BIT(0)
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/*
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* CRD1[b5]: DP MCU FW is executing
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* CRDC[b0]: DP link success
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* CRDF[b0]: DP HPD
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* CRE5[b0]: Host reading EDID process is done
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*/
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#define ASTDP_MCU_FW_EXECUTING BIT(5)
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#define ASTDP_LINK_SUCCESS BIT(0)
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#define ASTDP_HPD BIT(0)
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#define ASTDP_HOST_EDID_READ_DONE BIT(0)
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#define ASTDP_HOST_EDID_READ_DONE_MASK GENMASK(0, 0)
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/*
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* CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE
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* Precondition: A. ~AST_DP_PHY_SLEEP &&
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* B. DP_HPD &&
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* C. DP_LINK_SUCCESS
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*/
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#define ASTDP_MIRROR_VIDEO_ENABLE BIT(4)
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#define ASTDP_EDID_READ_POINTER_MASK GENMASK(7, 0)
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#define ASTDP_EDID_VALID_FLAG_MASK GENMASK(0, 0)
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#define ASTDP_EDID_READ_DATA_MASK GENMASK(7, 0)
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/*
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* ASTDP setmode registers:
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* CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp)
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* CRE1[7:0]: MISC1 (default: 0x00)
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* CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50)
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*/
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#define ASTDP_MISC0_24bpp BIT(5)
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#define ASTDP_MISC1 0
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#define ASTDP_AND_CLEAR_MASK 0x00
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#endif
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