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PECI clock divider is programmed on 10:8 bits of PECI Control register. Before setting a new value, clear bits read from hardware. Reviewed-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20240417134849.5793-1-iwona.winiarska@intel.com Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>