ae47ee5fc4
Evaluate the desired pixel clock polarity from the device tree. Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
19 lines
338 B
C
19 lines
338 B
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
#ifndef MT9P031_H
|
|
#define MT9P031_H
|
|
|
|
struct v4l2_subdev;
|
|
|
|
/*
|
|
* struct mt9p031_platform_data - MT9P031 platform data
|
|
* @ext_freq: Input clock frequency
|
|
* @target_freq: Pixel clock frequency
|
|
*/
|
|
struct mt9p031_platform_data {
|
|
unsigned int pixclk_pol:1;
|
|
int ext_freq;
|
|
int target_freq;
|
|
};
|
|
|
|
#endif
|