Implement a simple static mapping algorithm of the i915 priority levels (int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as follows: i915 level < 0 -> GuC low level (3) i915 level == 0 -> GuC normal level (2) i915 level < INT_MAX -> GuC high level (1) i915 level == INT_MAX -> GuC highest level (0) We believe this mapping should cover the UMD use cases (3 distinct user levels + 1 kernel level). In addition to static mapping, a simple counter system is attached to each context tracking the number of requests inflight on the context at each level. This is needed as the GuC levels are per context while in the i915 levels are per request. v2: (Daniele) - Add BUILD_BUG_ON to enforce ordering of priority levels - Add missing lockdep to guc_prio_fini - Check for return before setting context registered flag - Map DISPLAY priority or higher to highest guc prio - Update comment for guc_prio Signed-off-by: Matthew Brost <matthew.brost@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210727002348.97202-33-matthew.brost@intel.com
519 lines
13 KiB
C
519 lines
13 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2015-2021 Intel Corporation
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*/
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#include <linux/kthread.h>
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#include <trace/events/dma_fence.h>
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#include <uapi/linux/sched/types.h>
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_breadcrumbs.h"
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#include "intel_context.h"
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#include "intel_engine_pm.h"
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#include "intel_gt_pm.h"
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#include "intel_gt_requests.h"
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static bool irq_enable(struct intel_breadcrumbs *b)
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{
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return intel_engine_irq_enable(b->irq_engine);
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}
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static void irq_disable(struct intel_breadcrumbs *b)
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{
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intel_engine_irq_disable(b->irq_engine);
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}
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static void __intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b)
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{
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/*
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* Since we are waiting on a request, the GPU should be busy
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* and should have its own rpm reference.
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*/
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if (GEM_WARN_ON(!intel_gt_pm_get_if_awake(b->irq_engine->gt)))
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return;
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/*
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* The breadcrumb irq will be disarmed on the interrupt after the
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* waiters are signaled. This gives us a single interrupt window in
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* which we can add a new waiter and avoid the cost of re-enabling
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* the irq.
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*/
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WRITE_ONCE(b->irq_armed, true);
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/* Requests may have completed before we could enable the interrupt. */
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if (!b->irq_enabled++ && b->irq_enable(b))
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irq_work_queue(&b->irq_work);
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}
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static void intel_breadcrumbs_arm_irq(struct intel_breadcrumbs *b)
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{
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if (!b->irq_engine)
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return;
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spin_lock(&b->irq_lock);
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if (!b->irq_armed)
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__intel_breadcrumbs_arm_irq(b);
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spin_unlock(&b->irq_lock);
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}
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static void __intel_breadcrumbs_disarm_irq(struct intel_breadcrumbs *b)
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{
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GEM_BUG_ON(!b->irq_enabled);
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if (!--b->irq_enabled)
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b->irq_disable(b);
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WRITE_ONCE(b->irq_armed, false);
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intel_gt_pm_put_async(b->irq_engine->gt);
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}
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static void intel_breadcrumbs_disarm_irq(struct intel_breadcrumbs *b)
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{
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spin_lock(&b->irq_lock);
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if (b->irq_armed)
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__intel_breadcrumbs_disarm_irq(b);
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spin_unlock(&b->irq_lock);
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}
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static void add_signaling_context(struct intel_breadcrumbs *b,
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struct intel_context *ce)
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{
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lockdep_assert_held(&ce->signal_lock);
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spin_lock(&b->signalers_lock);
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list_add_rcu(&ce->signal_link, &b->signalers);
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spin_unlock(&b->signalers_lock);
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}
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static bool remove_signaling_context(struct intel_breadcrumbs *b,
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struct intel_context *ce)
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{
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lockdep_assert_held(&ce->signal_lock);
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if (!list_empty(&ce->signals))
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return false;
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spin_lock(&b->signalers_lock);
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list_del_rcu(&ce->signal_link);
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spin_unlock(&b->signalers_lock);
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return true;
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}
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__maybe_unused static bool
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check_signal_order(struct intel_context *ce, struct i915_request *rq)
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{
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if (rq->context != ce)
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return false;
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if (!list_is_last(&rq->signal_link, &ce->signals) &&
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i915_seqno_passed(rq->fence.seqno,
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list_next_entry(rq, signal_link)->fence.seqno))
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return false;
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if (!list_is_first(&rq->signal_link, &ce->signals) &&
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i915_seqno_passed(list_prev_entry(rq, signal_link)->fence.seqno,
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rq->fence.seqno))
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return false;
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return true;
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}
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static bool
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__dma_fence_signal(struct dma_fence *fence)
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{
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return !test_and_set_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags);
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}
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static void
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__dma_fence_signal__timestamp(struct dma_fence *fence, ktime_t timestamp)
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{
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fence->timestamp = timestamp;
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set_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags);
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trace_dma_fence_signaled(fence);
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}
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static void
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__dma_fence_signal__notify(struct dma_fence *fence,
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const struct list_head *list)
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{
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struct dma_fence_cb *cur, *tmp;
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lockdep_assert_held(fence->lock);
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list_for_each_entry_safe(cur, tmp, list, node) {
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INIT_LIST_HEAD(&cur->node);
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cur->func(fence, cur);
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}
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}
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static void add_retire(struct intel_breadcrumbs *b, struct intel_timeline *tl)
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{
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if (b->irq_engine)
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intel_engine_add_retire(b->irq_engine, tl);
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}
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static struct llist_node *
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slist_add(struct llist_node *node, struct llist_node *head)
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{
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node->next = head;
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return node;
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}
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static void signal_irq_work(struct irq_work *work)
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{
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struct intel_breadcrumbs *b = container_of(work, typeof(*b), irq_work);
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const ktime_t timestamp = ktime_get();
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struct llist_node *signal, *sn;
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struct intel_context *ce;
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signal = NULL;
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if (unlikely(!llist_empty(&b->signaled_requests)))
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signal = llist_del_all(&b->signaled_requests);
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/*
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* Keep the irq armed until the interrupt after all listeners are gone.
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*
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* Enabling/disabling the interrupt is rather costly, roughly a couple
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* of hundred microseconds. If we are proactive and enable/disable
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* the interrupt around every request that wants a breadcrumb, we
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* quickly drown in the extra orders of magnitude of latency imposed
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* on request submission.
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*
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* So we try to be lazy, and keep the interrupts enabled until no
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* more listeners appear within a breadcrumb interrupt interval (that
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* is until a request completes that no one cares about). The
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* observation is that listeners come in batches, and will often
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* listen to a bunch of requests in succession. Though note on icl+,
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* interrupts are always enabled due to concerns with rc6 being
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* dysfunctional with per-engine interrupt masking.
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*
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* We also try to avoid raising too many interrupts, as they may
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* be generated by userspace batches and it is unfortunately rather
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* too easy to drown the CPU under a flood of GPU interrupts. Thus
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* whenever no one appears to be listening, we turn off the interrupts.
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* Fewer interrupts should conserve power -- at the very least, fewer
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* interrupt draw less ire from other users of the system and tools
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* like powertop.
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*/
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if (!signal && READ_ONCE(b->irq_armed) && list_empty(&b->signalers))
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intel_breadcrumbs_disarm_irq(b);
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rcu_read_lock();
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atomic_inc(&b->signaler_active);
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list_for_each_entry_rcu(ce, &b->signalers, signal_link) {
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struct i915_request *rq;
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list_for_each_entry_rcu(rq, &ce->signals, signal_link) {
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bool release;
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if (!__i915_request_is_complete(rq))
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break;
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if (!test_and_clear_bit(I915_FENCE_FLAG_SIGNAL,
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&rq->fence.flags))
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break;
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/*
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* Queue for execution after dropping the signaling
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* spinlock as the callback chain may end up adding
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* more signalers to the same context or engine.
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*/
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spin_lock(&ce->signal_lock);
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list_del_rcu(&rq->signal_link);
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release = remove_signaling_context(b, ce);
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spin_unlock(&ce->signal_lock);
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if (release) {
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if (intel_timeline_is_last(ce->timeline, rq))
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add_retire(b, ce->timeline);
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intel_context_put(ce);
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}
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if (__dma_fence_signal(&rq->fence))
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/* We own signal_node now, xfer to local list */
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signal = slist_add(&rq->signal_node, signal);
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else
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i915_request_put(rq);
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}
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}
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atomic_dec(&b->signaler_active);
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rcu_read_unlock();
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llist_for_each_safe(signal, sn, signal) {
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struct i915_request *rq =
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llist_entry(signal, typeof(*rq), signal_node);
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struct list_head cb_list;
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if (rq->engine->sched_engine->retire_inflight_request_prio)
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rq->engine->sched_engine->retire_inflight_request_prio(rq);
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spin_lock(&rq->lock);
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list_replace(&rq->fence.cb_list, &cb_list);
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__dma_fence_signal__timestamp(&rq->fence, timestamp);
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__dma_fence_signal__notify(&rq->fence, &cb_list);
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spin_unlock(&rq->lock);
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i915_request_put(rq);
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}
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if (!READ_ONCE(b->irq_armed) && !list_empty(&b->signalers))
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intel_breadcrumbs_arm_irq(b);
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}
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struct intel_breadcrumbs *
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intel_breadcrumbs_create(struct intel_engine_cs *irq_engine)
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{
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struct intel_breadcrumbs *b;
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b = kzalloc(sizeof(*b), GFP_KERNEL);
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if (!b)
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return NULL;
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kref_init(&b->ref);
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spin_lock_init(&b->signalers_lock);
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INIT_LIST_HEAD(&b->signalers);
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init_llist_head(&b->signaled_requests);
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spin_lock_init(&b->irq_lock);
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init_irq_work(&b->irq_work, signal_irq_work);
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b->irq_engine = irq_engine;
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b->irq_enable = irq_enable;
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b->irq_disable = irq_disable;
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return b;
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}
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void intel_breadcrumbs_reset(struct intel_breadcrumbs *b)
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{
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unsigned long flags;
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if (!b->irq_engine)
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return;
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spin_lock_irqsave(&b->irq_lock, flags);
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if (b->irq_enabled)
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b->irq_enable(b);
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else
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b->irq_disable(b);
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spin_unlock_irqrestore(&b->irq_lock, flags);
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}
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void __intel_breadcrumbs_park(struct intel_breadcrumbs *b)
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{
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if (!READ_ONCE(b->irq_armed))
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return;
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/* Kick the work once more to drain the signalers, and disarm the irq */
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irq_work_sync(&b->irq_work);
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while (READ_ONCE(b->irq_armed) && !atomic_read(&b->active)) {
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local_irq_disable();
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signal_irq_work(&b->irq_work);
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local_irq_enable();
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cond_resched();
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}
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}
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void intel_breadcrumbs_free(struct kref *kref)
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{
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struct intel_breadcrumbs *b = container_of(kref, typeof(*b), ref);
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irq_work_sync(&b->irq_work);
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GEM_BUG_ON(!list_empty(&b->signalers));
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GEM_BUG_ON(b->irq_armed);
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kfree(b);
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}
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static void irq_signal_request(struct i915_request *rq,
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struct intel_breadcrumbs *b)
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{
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if (!__dma_fence_signal(&rq->fence))
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return;
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i915_request_get(rq);
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if (llist_add(&rq->signal_node, &b->signaled_requests))
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irq_work_queue(&b->irq_work);
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}
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static void insert_breadcrumb(struct i915_request *rq)
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{
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struct intel_breadcrumbs *b = READ_ONCE(rq->engine)->breadcrumbs;
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struct intel_context *ce = rq->context;
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struct list_head *pos;
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if (test_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags))
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return;
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/*
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* If the request is already completed, we can transfer it
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* straight onto a signaled list, and queue the irq worker for
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* its signal completion.
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*/
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if (__i915_request_is_complete(rq)) {
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irq_signal_request(rq, b);
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return;
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}
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if (list_empty(&ce->signals)) {
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intel_context_get(ce);
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add_signaling_context(b, ce);
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pos = &ce->signals;
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} else {
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/*
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* We keep the seqno in retirement order, so we can break
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* inside intel_engine_signal_breadcrumbs as soon as we've
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* passed the last completed request (or seen a request that
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* hasn't event started). We could walk the timeline->requests,
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* but keeping a separate signalers_list has the advantage of
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* hopefully being much smaller than the full list and so
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* provides faster iteration and detection when there are no
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* more interrupts required for this context.
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*
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* We typically expect to add new signalers in order, so we
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* start looking for our insertion point from the tail of
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* the list.
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*/
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list_for_each_prev(pos, &ce->signals) {
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struct i915_request *it =
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list_entry(pos, typeof(*it), signal_link);
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if (i915_seqno_passed(rq->fence.seqno, it->fence.seqno))
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break;
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}
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}
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i915_request_get(rq);
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list_add_rcu(&rq->signal_link, pos);
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GEM_BUG_ON(!check_signal_order(ce, rq));
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GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags));
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set_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags);
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/*
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* Defer enabling the interrupt to after HW submission and recheck
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* the request as it may have completed and raised the interrupt as
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* we were attaching it into the lists.
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*/
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irq_work_queue(&b->irq_work);
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}
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bool i915_request_enable_breadcrumb(struct i915_request *rq)
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{
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struct intel_context *ce = rq->context;
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/* Serialises with i915_request_retire() using rq->lock */
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if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
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return true;
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/*
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* Peek at i915_request_submit()/i915_request_unsubmit() status.
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*
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* If the request is not yet active (and not signaled), we will
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* attach the breadcrumb later.
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*/
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if (!test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags))
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return true;
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spin_lock(&ce->signal_lock);
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if (test_bit(I915_FENCE_FLAG_ACTIVE, &rq->fence.flags))
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insert_breadcrumb(rq);
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spin_unlock(&ce->signal_lock);
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return true;
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}
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void i915_request_cancel_breadcrumb(struct i915_request *rq)
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{
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struct intel_breadcrumbs *b = READ_ONCE(rq->engine)->breadcrumbs;
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struct intel_context *ce = rq->context;
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bool release;
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spin_lock(&ce->signal_lock);
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if (!test_and_clear_bit(I915_FENCE_FLAG_SIGNAL, &rq->fence.flags)) {
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spin_unlock(&ce->signal_lock);
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return;
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}
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list_del_rcu(&rq->signal_link);
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release = remove_signaling_context(b, ce);
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spin_unlock(&ce->signal_lock);
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if (release)
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intel_context_put(ce);
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if (__i915_request_is_complete(rq))
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irq_signal_request(rq, b);
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i915_request_put(rq);
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}
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void intel_context_remove_breadcrumbs(struct intel_context *ce,
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struct intel_breadcrumbs *b)
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{
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struct i915_request *rq, *rn;
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bool release = false;
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unsigned long flags;
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spin_lock_irqsave(&ce->signal_lock, flags);
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if (list_empty(&ce->signals))
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goto unlock;
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list_for_each_entry_safe(rq, rn, &ce->signals, signal_link) {
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GEM_BUG_ON(!__i915_request_is_complete(rq));
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if (!test_and_clear_bit(I915_FENCE_FLAG_SIGNAL,
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&rq->fence.flags))
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continue;
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list_del_rcu(&rq->signal_link);
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irq_signal_request(rq, b);
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i915_request_put(rq);
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}
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release = remove_signaling_context(b, ce);
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unlock:
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spin_unlock_irqrestore(&ce->signal_lock, flags);
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if (release)
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intel_context_put(ce);
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while (atomic_read(&b->signaler_active))
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cpu_relax();
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}
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static void print_signals(struct intel_breadcrumbs *b, struct drm_printer *p)
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{
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struct intel_context *ce;
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struct i915_request *rq;
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drm_printf(p, "Signals:\n");
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rcu_read_lock();
|
|
list_for_each_entry_rcu(ce, &b->signalers, signal_link) {
|
|
list_for_each_entry_rcu(rq, &ce->signals, signal_link)
|
|
drm_printf(p, "\t[%llx:%llx%s] @ %dms\n",
|
|
rq->fence.context, rq->fence.seqno,
|
|
__i915_request_is_complete(rq) ? "!" :
|
|
__i915_request_has_started(rq) ? "*" :
|
|
"",
|
|
jiffies_to_msecs(jiffies - rq->emitted_jiffies));
|
|
}
|
|
rcu_read_unlock();
|
|
}
|
|
|
|
void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine,
|
|
struct drm_printer *p)
|
|
{
|
|
struct intel_breadcrumbs *b;
|
|
|
|
b = engine->breadcrumbs;
|
|
if (!b)
|
|
return;
|
|
|
|
drm_printf(p, "IRQ: %s\n", enableddisabled(b->irq_armed));
|
|
if (!list_empty(&b->signalers))
|
|
print_signals(b, p);
|
|
}
|