linux/arch/arm64/include
Will Deacon 0113340e6e arm64: cpufeature: Spell out register fields for ID_ISAR4 and ID_PFR1
In preparation for runtime updates to the strictness of some AArch32
features, spell out the register fields for ID_ISAR4 and ID_PFR1 to make
things clearer to read. Note that this isn't functionally necessary, as
the feature arrays themselves are not modified dynamically and remain
'const'.

Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20200421142922.18950-3-will@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
2020-04-28 14:23:18 +01:00
..
asm arm64: cpufeature: Spell out register fields for ID_ISAR4 and ID_PFR1 2020-04-28 14:23:18 +01:00
uapi/asm ARM: Cleanups and corner case fixes 2020-01-31 09:30:41 -08:00