65c9ad77cb
Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules to allow auto-load at boot. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-50-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
123 lines
3.5 KiB
C
123 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* James Liao <jamesjj.liao@mediatek.com>
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* Fabien Parent <fparent@baylibre.com>
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*
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* Copyright (c) 2023 Collabora, Ltd.
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/clock/mt8516-clk.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-pll.h"
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#define MT8516_PLL_FMAX (1502UL * MHZ)
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#define CON0_MT8516_RST_BAR BIT(27)
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#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
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_pcw_shift, _div_table) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.flags = _flags, \
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.rst_bar_mask = CON0_MT8516_RST_BAR, \
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.fmax = MT8516_PLL_FMAX, \
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.pcwbits = _pcwbits, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.div_table = _div_table, \
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}
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
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_pcw_shift) \
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PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
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NULL)
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static const struct mtk_pll_div_table mmpll_div_table[] = {
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{ .div = 0, .freq = MT8516_PLL_FMAX },
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{ .div = 1, .freq = 1000000000 },
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{ .div = 2, .freq = 604500000 },
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{ .div = 3, .freq = 253500000 },
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{ .div = 4, .freq = 126750000 },
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{ } /* sentinel */
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};
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static const struct mtk_pll_data plls[] = {
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PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0,
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21, 0x0104, 24, 0, 0x0104, 0),
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PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
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HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
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PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000,
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HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
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PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0,
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21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
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PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0,
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31, 0x0180, 1, 0x0194, 0x0184, 0),
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PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0,
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31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
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};
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static int clk_mt8516_apmixed_probe(struct platform_device *pdev)
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{
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void __iomem *base;
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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int ret;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
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if (ret)
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return ret;
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ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (ret)
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goto unregister_plls;
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return 0;
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unregister_plls:
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mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
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return ret;
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}
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static const struct of_device_id of_match_clk_mt8516_apmixed[] = {
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{ .compatible = "mediatek,mt8516-apmixedsys" },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8516_apmixed);
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static struct platform_driver clk_mt8516_apmixed_drv = {
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.probe = clk_mt8516_apmixed_probe,
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.driver = {
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.name = "clk-mt8516-apmixed",
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.of_match_table = of_match_clk_mt8516_apmixed,
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},
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};
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builtin_platform_driver(clk_mt8516_apmixed_drv)
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MODULE_DESCRIPTION("MediaTek MT8516 apmixedsys clocks driver");
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MODULE_LICENSE("GPL");
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