ef98682a4e
Add devicetree binding for Bitmain BM1880 SoC reset controller. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2018 Bitmain Ltd.
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* Copyright (c) 2019 Linaro Ltd.
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*/
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#ifndef _DT_BINDINGS_BM1880_RESET_H
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#define _DT_BINDINGS_BM1880_RESET_H
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#define BM1880_RST_MAIN_AP 0
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#define BM1880_RST_SECOND_AP 1
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#define BM1880_RST_DDR 2
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#define BM1880_RST_VIDEO 3
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#define BM1880_RST_JPEG 4
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#define BM1880_RST_VPP 5
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#define BM1880_RST_GDMA 6
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#define BM1880_RST_AXI_SRAM 7
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#define BM1880_RST_TPU 8
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#define BM1880_RST_USB 9
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#define BM1880_RST_ETH0 10
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#define BM1880_RST_ETH1 11
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#define BM1880_RST_NAND 12
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#define BM1880_RST_EMMC 13
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#define BM1880_RST_SD 14
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#define BM1880_RST_SDMA 15
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#define BM1880_RST_I2S0 16
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#define BM1880_RST_I2S1 17
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#define BM1880_RST_UART0_1_CLK 18
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#define BM1880_RST_UART0_1_ACLK 19
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#define BM1880_RST_UART2_3_CLK 20
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#define BM1880_RST_UART2_3_ACLK 21
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#define BM1880_RST_MINER 22
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#define BM1880_RST_I2C0 23
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#define BM1880_RST_I2C1 24
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#define BM1880_RST_I2C2 25
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#define BM1880_RST_I2C3 26
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#define BM1880_RST_I2C4 27
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#define BM1880_RST_PWM0 28
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#define BM1880_RST_PWM1 29
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#define BM1880_RST_PWM2 30
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#define BM1880_RST_PWM3 31
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#define BM1880_RST_SPI 32
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#define BM1880_RST_GPIO0 33
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#define BM1880_RST_GPIO1 34
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#define BM1880_RST_GPIO2 35
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#define BM1880_RST_EFUSE 36
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#define BM1880_RST_WDT 37
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#define BM1880_RST_AHB_ROM 38
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#define BM1880_RST_SPIC 39
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#endif /* _DT_BINDINGS_BM1880_RESET_H */
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