02b4e2756e
All ARMv5 and older CPUs invalidate their caches in the early assembly setup function, prior to enabling the MMU. This is because the L1 cache should not contain any data relevant to the execution of the kernel at this point; all data should have been flushed out to memory. This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed, these typically do not search their caches when caching is disabled (as it needs to be when the MMU is disabled) so this change should be safe. ARMv7 allows there to be CPUs which search their caches while caching is disabled, and it's permitted that the cache is uninitialised at boot; for these, the architecture reference manual requires that an implementation specific code sequence is used immediately after reset to ensure that the cache is placed into a sane state. Such functionality is definitely outside the remit of the Linux kernel, and must be done by the SoC's firmware before _any_ CPU gets to the Linux kernel. Changing the data cache clean+invalidate to a mere invalidate allows us to get rid of a lot of platform specific hacks around this issue for their secondary CPU bringup paths - some of which were buggy. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
637 lines
19 KiB
ArmAsm
637 lines
19 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-v7.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is the "shell" of the ARMv7 processor support.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include "proc-macros.S"
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#ifdef CONFIG_ARM_LPAE
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#include "proc-v7-3level.S"
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#else
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#include "proc-v7-2level.S"
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#endif
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ENTRY(cpu_v7_proc_init)
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ret lr
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ENDPROC(cpu_v7_proc_init)
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ENTRY(cpu_v7_proc_fin)
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x0006 @ .............ca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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ret lr
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ENDPROC(cpu_v7_proc_fin)
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/*
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* cpu_v7_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* - loc - location to jump to for soft reset
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*
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* This code must be executed using a flat identity mapping with
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* caches disabled.
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_v7_reset)
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mrc p15, 0, r1, c1, c0, 0 @ ctrl register
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bic r1, r1, #0x1 @ ...............m
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THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
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mcr p15, 0, r1, c1, c0, 0 @ disable MMU
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isb
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bx r0
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ENDPROC(cpu_v7_reset)
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.popsection
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/*
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* cpu_v7_do_idle()
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*
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* Idle the processor (eg, wait for interrupt).
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*
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* IRQs are already disabled.
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*/
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ENTRY(cpu_v7_do_idle)
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dsb @ WFI may enter a low-power mode
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wfi
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ret lr
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ENDPROC(cpu_v7_do_idle)
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ENTRY(cpu_v7_dcache_clean_area)
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ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
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ALT_UP_B(1f)
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ret lr
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1: dcache_line_size r2, r3
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2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, r2
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subs r1, r1, r2
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bhi 2b
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dsb ishst
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ret lr
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ENDPROC(cpu_v7_dcache_clean_area)
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string cpu_v7_name, "ARMv7 Processor"
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.align
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/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
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.globl cpu_v7_suspend_size
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.equ cpu_v7_suspend_size, 4 * 9
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#ifdef CONFIG_ARM_CPU_SUSPEND
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ENTRY(cpu_v7_do_suspend)
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stmfd sp!, {r4 - r10, lr}
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mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
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stmia r0!, {r4 - r5}
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#ifdef CONFIG_MMU
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mrc p15, 0, r6, c3, c0, 0 @ Domain ID
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#ifdef CONFIG_ARM_LPAE
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mrrc p15, 1, r5, r7, c2 @ TTB 1
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#else
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mrc p15, 0, r7, c2, c0, 1 @ TTB 1
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#endif
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mrc p15, 0, r11, c2, c0, 2 @ TTB control register
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#endif
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mrc p15, 0, r8, c1, c0, 0 @ Control register
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mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
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mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
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stmia r0, {r5 - r11}
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ldmfd sp!, {r4 - r10, pc}
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ENDPROC(cpu_v7_do_suspend)
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ENTRY(cpu_v7_do_resume)
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
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ldmia r0!, {r4 - r5}
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
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ldmia r0, {r5 - r11}
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r6, c3, c0, 0 @ Domain ID
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#ifdef CONFIG_ARM_LPAE
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mcrr p15, 0, r1, ip, c2 @ TTB 0
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mcrr p15, 1, r5, r7, c2 @ TTB 1
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#else
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ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
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ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
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mcr p15, 0, r1, c2, c0, 0 @ TTB 0
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mcr p15, 0, r7, c2, c0, 1 @ TTB 1
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#endif
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mcr p15, 0, r11, c2, c0, 2 @ TTB control register
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ldr r4, =PRRR @ PRRR
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ldr r5, =NMRR @ NMRR
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mcr p15, 0, r4, c10, c2, 0 @ write PRRR
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mcr p15, 0, r5, c10, c2, 1 @ write NMRR
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#endif /* CONFIG_MMU */
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mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
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teq r4, r9 @ Is it already set?
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mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
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mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
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isb
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dsb
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mov r0, r8 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_v7_do_resume)
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#endif
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/*
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* Cortex-A8
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*/
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globl_equ cpu_ca8_proc_init, cpu_v7_proc_init
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globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin
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globl_equ cpu_ca8_reset, cpu_v7_reset
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globl_equ cpu_ca8_do_idle, cpu_v7_do_idle
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globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
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globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext
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globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size
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#ifdef CONFIG_ARM_CPU_SUSPEND
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globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend
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globl_equ cpu_ca8_do_resume, cpu_v7_do_resume
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#endif
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/*
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* Cortex-A9 processor functions
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*/
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globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init
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globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin
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globl_equ cpu_ca9mp_reset, cpu_v7_reset
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globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle
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globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
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globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm
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globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext
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.globl cpu_ca9mp_suspend_size
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.equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
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#ifdef CONFIG_ARM_CPU_SUSPEND
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ENTRY(cpu_ca9mp_do_suspend)
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stmfd sp!, {r4 - r5}
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mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
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mrc p15, 0, r5, c15, c0, 0 @ Power register
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stmia r0!, {r4 - r5}
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ldmfd sp!, {r4 - r5}
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b cpu_v7_do_suspend
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ENDPROC(cpu_ca9mp_do_suspend)
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ENTRY(cpu_ca9mp_do_resume)
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ldmia r0!, {r4 - r5}
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mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
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teq r4, r10 @ Already restored?
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mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
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mrc p15, 0, r10, c15, c0, 0 @ Read Power register
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teq r5, r10 @ Already restored?
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mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
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b cpu_v7_do_resume
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ENDPROC(cpu_ca9mp_do_resume)
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#endif
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#ifdef CONFIG_CPU_PJ4B
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globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
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globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
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globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
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globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
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globl_equ cpu_pj4b_reset, cpu_v7_reset
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#ifdef CONFIG_PJ4B_ERRATA_4742
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ENTRY(cpu_pj4b_do_idle)
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dsb @ WFI may enter a low-power mode
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wfi
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dsb @barrier
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ret lr
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ENDPROC(cpu_pj4b_do_idle)
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#else
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globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
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#endif
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globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
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#ifdef CONFIG_ARM_CPU_SUSPEND
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ENTRY(cpu_pj4b_do_suspend)
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stmfd sp!, {r6 - r10}
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mrc p15, 1, r6, c15, c1, 0 @ save CP15 - extra features
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mrc p15, 1, r7, c15, c2, 0 @ save CP15 - Aux Func Modes Ctrl 0
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mrc p15, 1, r8, c15, c1, 2 @ save CP15 - Aux Debug Modes Ctrl 2
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mrc p15, 1, r9, c15, c1, 1 @ save CP15 - Aux Debug Modes Ctrl 1
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mrc p15, 0, r10, c9, c14, 0 @ save CP15 - PMC
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stmia r0!, {r6 - r10}
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ldmfd sp!, {r6 - r10}
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b cpu_v7_do_suspend
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ENDPROC(cpu_pj4b_do_suspend)
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ENTRY(cpu_pj4b_do_resume)
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ldmia r0!, {r6 - r10}
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mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features
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mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0
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mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
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mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1
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mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC
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b cpu_v7_do_resume
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ENDPROC(cpu_pj4b_do_resume)
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#endif
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.globl cpu_pj4b_suspend_size
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.equ cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
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#endif
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/*
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* __v7_setup
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*
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* Initialise TLB, Caches, and MMU state ready to switch the MMU
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* on. Return in r0 the new CP15 C1 control register setting.
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*
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* This should be able to cover all ARMv7 cores.
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*
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* It is assumed that:
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* - cache type register is implemented
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*/
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__v7_ca5mp_setup:
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__v7_ca9mp_setup:
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__v7_cr7mp_setup:
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mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
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b 1f
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__v7_ca7mp_setup:
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__v7_ca12mp_setup:
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__v7_ca15mp_setup:
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__v7_b15mp_setup:
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__v7_ca17mp_setup:
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mov r10, #0
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1:
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#ifdef CONFIG_SMP
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ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
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ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
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tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
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orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
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orreq r0, r0, r10 @ Enable CPU-specific SMP bits
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mcreq p15, 0, r0, c1, c0, 1
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#endif
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b __v7_setup
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__v7_pj4b_setup:
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#ifdef CONFIG_CPU_PJ4B
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/* Auxiliary Debug Modes Control 1 Register */
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#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
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#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
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#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
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/* Auxiliary Debug Modes Control 2 Register */
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#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
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#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
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#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
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#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
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#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
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#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
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PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
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/* Auxiliary Functional Modes Control Register 0 */
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#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
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#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
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#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
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/* Auxiliary Debug Modes Control 0 Register */
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#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
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/* Auxiliary Debug Modes Control 1 Register */
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mrc p15, 1, r0, c15, c1, 1
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orr r0, r0, #PJ4B_CLEAN_LINE
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orr r0, r0, #PJ4B_INTER_PARITY
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bic r0, r0, #PJ4B_STATIC_BP
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mcr p15, 1, r0, c15, c1, 1
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/* Auxiliary Debug Modes Control 2 Register */
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mrc p15, 1, r0, c15, c1, 2
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bic r0, r0, #PJ4B_FAST_LDR
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orr r0, r0, #PJ4B_AUX_DBG_CTRL2
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mcr p15, 1, r0, c15, c1, 2
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/* Auxiliary Functional Modes Control Register 0 */
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mrc p15, 1, r0, c15, c2, 0
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#ifdef CONFIG_SMP
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orr r0, r0, #PJ4B_SMP_CFB
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#endif
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orr r0, r0, #PJ4B_L1_PAR_CHK
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orr r0, r0, #PJ4B_BROADCAST_CACHE
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mcr p15, 1, r0, c15, c2, 0
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/* Auxiliary Debug Modes Control 0 Register */
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mrc p15, 1, r0, c15, c1, 0
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orr r0, r0, #PJ4B_WFI_WFE
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mcr p15, 1, r0, c15, c1, 0
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#endif /* CONFIG_CPU_PJ4B */
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__v7_setup:
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adr r12, __v7_setup_stack @ the local stack
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stmia r12, {r0-r5, r7, r9, r11, lr}
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bl v7_invalidate_l1
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ldmia r12, {r0-r5, r7, r9, r11, lr}
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mrc p15, 0, r0, c0, c0, 0 @ read main ID register
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and r10, r0, #0xff000000 @ ARM?
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teq r10, #0x41000000
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bne 3f
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and r5, r0, #0x00f00000 @ variant
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and r6, r0, #0x0000000f @ revision
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orr r6, r6, r5, lsr #20-4 @ combine variant and revision
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ubfx r0, r0, #4, #12 @ primary part number
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/* Cortex-A8 Errata */
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ldr r10, =0x00000c08 @ Cortex-A8 primary part number
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teq r0, r10
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bne 2f
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#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
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teq r5, #0x00100000 @ only present in r1p*
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mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
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orreq r10, r10, #(1 << 6) @ set IBE to 1
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mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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#ifdef CONFIG_ARM_ERRATA_458693
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teq r6, #0x20 @ only present in r2p0
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mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
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orreq r10, r10, #(1 << 5) @ set L1NEON to 1
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orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
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mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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#ifdef CONFIG_ARM_ERRATA_460075
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teq r6, #0x20 @ only present in r2p0
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mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
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tsteq r10, #1 << 22
|
|
orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
|
|
mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
|
|
#endif
|
|
b 3f
|
|
|
|
/* Cortex-A9 Errata */
|
|
2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
|
|
teq r0, r10
|
|
bne 3f
|
|
#ifdef CONFIG_ARM_ERRATA_742230
|
|
cmp r6, #0x22 @ only present up to r2p2
|
|
mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
|
|
orrle r10, r10, #1 << 4 @ set bit #4
|
|
mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
|
|
#endif
|
|
#ifdef CONFIG_ARM_ERRATA_742231
|
|
teq r6, #0x20 @ present in r2p0
|
|
teqne r6, #0x21 @ present in r2p1
|
|
teqne r6, #0x22 @ present in r2p2
|
|
mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
|
|
orreq r10, r10, #1 << 12 @ set bit #12
|
|
orreq r10, r10, #1 << 22 @ set bit #22
|
|
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
|
|
#endif
|
|
#ifdef CONFIG_ARM_ERRATA_743622
|
|
teq r5, #0x00200000 @ only present in r2p*
|
|
mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
|
|
orreq r10, r10, #1 << 6 @ set bit #6
|
|
mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
|
|
#endif
|
|
#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
|
|
ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
|
|
ALT_UP_B(1f)
|
|
mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
|
|
orrlt r10, r10, #1 << 11 @ set bit #11
|
|
mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
|
|
1:
|
|
#endif
|
|
|
|
/* Cortex-A15 Errata */
|
|
3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
|
|
teq r0, r10
|
|
bne 4f
|
|
|
|
#ifdef CONFIG_ARM_ERRATA_773022
|
|
cmp r6, #0x4 @ only present up to r0p4
|
|
mrcle p15, 0, r10, c1, c0, 1 @ read aux control register
|
|
orrle r10, r10, #1 << 1 @ disable loop buffer
|
|
mcrle p15, 0, r10, c1, c0, 1 @ write aux control register
|
|
#endif
|
|
|
|
4: mov r10, #0
|
|
mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
|
|
#ifdef CONFIG_MMU
|
|
mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
|
|
v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
|
|
ldr r5, =PRRR @ PRRR
|
|
ldr r6, =NMRR @ NMRR
|
|
mcr p15, 0, r5, c10, c2, 0 @ write PRRR
|
|
mcr p15, 0, r6, c10, c2, 1 @ write NMRR
|
|
#endif
|
|
dsb @ Complete invalidations
|
|
#ifndef CONFIG_ARM_THUMBEE
|
|
mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
|
|
and r0, r0, #(0xf << 12) @ ThumbEE enabled field
|
|
teq r0, #(1 << 12) @ check if ThumbEE is present
|
|
bne 1f
|
|
mov r5, #0
|
|
mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
|
|
mrc p14, 6, r0, c0, c0, 0 @ load TEECR
|
|
orr r0, r0, #1 @ set the 1st bit in order to
|
|
mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
|
|
1:
|
|
#endif
|
|
adr r5, v7_crval
|
|
ldmia r5, {r5, r6}
|
|
ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
|
|
#ifdef CONFIG_SWP_EMULATE
|
|
orr r5, r5, #(1 << 10) @ set SW bit in "clear"
|
|
bic r6, r6, #(1 << 10) @ clear it in "mmuset"
|
|
#endif
|
|
mrc p15, 0, r0, c1, c0, 0 @ read control register
|
|
bic r0, r0, r5 @ clear bits them
|
|
orr r0, r0, r6 @ set them
|
|
THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
|
|
ret lr @ return to head.S:__ret
|
|
ENDPROC(__v7_setup)
|
|
|
|
.align 2
|
|
__v7_setup_stack:
|
|
.space 4 * 11 @ 11 registers
|
|
|
|
__INITDATA
|
|
|
|
@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
|
|
define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
|
|
#ifndef CONFIG_ARM_LPAE
|
|
define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
|
|
define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
|
|
#endif
|
|
#ifdef CONFIG_CPU_PJ4B
|
|
define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
|
|
#endif
|
|
|
|
.section ".rodata"
|
|
|
|
string cpu_arch_name, "armv7"
|
|
string cpu_elf_name, "v7"
|
|
.align
|
|
|
|
.section ".proc.info.init", #alloc
|
|
|
|
/*
|
|
* Standard v7 proc info content
|
|
*/
|
|
.macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
|
|
ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
|
|
PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
|
|
ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
|
|
PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
|
|
.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
|
|
initfn \initfunc, \name
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
|
|
HWCAP_EDSP | HWCAP_TLS | \hwcaps
|
|
.long cpu_v7_name
|
|
.long \proc_fns
|
|
.long v7wbi_tlb_fns
|
|
.long v6_user_fns
|
|
.long v7_cache_fns
|
|
.endm
|
|
|
|
#ifndef CONFIG_ARM_LPAE
|
|
/*
|
|
* ARM Ltd. Cortex A5 processor.
|
|
*/
|
|
.type __v7_ca5mp_proc_info, #object
|
|
__v7_ca5mp_proc_info:
|
|
.long 0x410fc050
|
|
.long 0xff0ffff0
|
|
__v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup
|
|
.size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
|
|
|
|
/*
|
|
* ARM Ltd. Cortex A9 processor.
|
|
*/
|
|
.type __v7_ca9mp_proc_info, #object
|
|
__v7_ca9mp_proc_info:
|
|
.long 0x410fc090
|
|
.long 0xff0ffff0
|
|
__v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
|
|
.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
|
|
|
|
/*
|
|
* ARM Ltd. Cortex A8 processor.
|
|
*/
|
|
.type __v7_ca8_proc_info, #object
|
|
__v7_ca8_proc_info:
|
|
.long 0x410fc080
|
|
.long 0xff0ffff0
|
|
__v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
|
|
.size __v7_ca8_proc_info, . - __v7_ca8_proc_info
|
|
|
|
#endif /* CONFIG_ARM_LPAE */
|
|
|
|
/*
|
|
* Marvell PJ4B processor.
|
|
*/
|
|
#ifdef CONFIG_CPU_PJ4B
|
|
.type __v7_pj4b_proc_info, #object
|
|
__v7_pj4b_proc_info:
|
|
.long 0x560f5800
|
|
.long 0xff0fff00
|
|
__v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions
|
|
.size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
|
|
#endif
|
|
|
|
/*
|
|
* ARM Ltd. Cortex R7 processor.
|
|
*/
|
|
.type __v7_cr7mp_proc_info, #object
|
|
__v7_cr7mp_proc_info:
|
|
.long 0x410fc170
|
|
.long 0xff0ffff0
|
|
__v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
|
|
.size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
|
|
|
|
/*
|
|
* ARM Ltd. Cortex A7 processor.
|
|
*/
|
|
.type __v7_ca7mp_proc_info, #object
|
|
__v7_ca7mp_proc_info:
|
|
.long 0x410fc070
|
|
.long 0xff0ffff0
|
|
__v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup
|
|
.size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
|
|
|
|
/*
|
|
* ARM Ltd. Cortex A12 processor.
|
|
*/
|
|
.type __v7_ca12mp_proc_info, #object
|
|
__v7_ca12mp_proc_info:
|
|
.long 0x410fc0d0
|
|
.long 0xff0ffff0
|
|
__v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup
|
|
.size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
|
|
|
|
/*
|
|
* ARM Ltd. Cortex A15 processor.
|
|
*/
|
|
.type __v7_ca15mp_proc_info, #object
|
|
__v7_ca15mp_proc_info:
|
|
.long 0x410fc0f0
|
|
.long 0xff0ffff0
|
|
__v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup
|
|
.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
|
|
|
|
/*
|
|
* Broadcom Corporation Brahma-B15 processor.
|
|
*/
|
|
.type __v7_b15mp_proc_info, #object
|
|
__v7_b15mp_proc_info:
|
|
.long 0x420f00f0
|
|
.long 0xff0ffff0
|
|
__v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup
|
|
.size __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
|
|
|
|
/*
|
|
* ARM Ltd. Cortex A17 processor.
|
|
*/
|
|
.type __v7_ca17mp_proc_info, #object
|
|
__v7_ca17mp_proc_info:
|
|
.long 0x410fc0e0
|
|
.long 0xff0ffff0
|
|
__v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup
|
|
.size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
|
|
|
|
/*
|
|
* Qualcomm Inc. Krait processors.
|
|
*/
|
|
.type __krait_proc_info, #object
|
|
__krait_proc_info:
|
|
.long 0x510f0400 @ Required ID value
|
|
.long 0xff0ffc00 @ Mask for ID
|
|
/*
|
|
* Some Krait processors don't indicate support for SDIV and UDIV
|
|
* instructions in the ARM instruction set, even though they actually
|
|
* do support them. They also don't indicate support for fused multiply
|
|
* instructions even though they actually do support them.
|
|
*/
|
|
__v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
|
|
.size __krait_proc_info, . - __krait_proc_info
|
|
|
|
/*
|
|
* Match any ARMv7 processor core.
|
|
*/
|
|
.type __v7_proc_info, #object
|
|
__v7_proc_info:
|
|
.long 0x000f0000 @ Required ID value
|
|
.long 0x000f0000 @ Mask for ID
|
|
__v7_proc __v7_proc_info, __v7_setup
|
|
.size __v7_proc_info, . - __v7_proc_info
|