02ec75edaa
access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controller. It allows an accurate representation of the hardware, where various peripherals are connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
252 lines
7.1 KiB
YAML
252 lines
7.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mmc/arm,pl18x.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM PrimeCell MultiMedia Card Interface (MMCI) PL180 and PL181
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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- Ulf Hansson <ulf.hansson@linaro.org>
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description:
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The ARM PrimeCells MMCI PL180 and PL181 provides an interface for
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reading and writing to MultiMedia and SD cards alike. Over the years
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vendors have use the VHDL code from ARM to create derivative MMC/SD/SDIO
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host controllers with very similar characteristics.
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allOf:
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- $ref: /schemas/arm/primecell.yaml#
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- $ref: mmc-controller.yaml#
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# We need a select here so we don't match all nodes with 'arm,primecell'
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select:
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properties:
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compatible:
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contains:
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enum:
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- arm,pl180
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- arm,pl181
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- arm,pl18x
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required:
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- compatible
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properties:
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compatible:
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oneOf:
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- description: The first version of the block, simply called
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PL180 and found in the ARM Integrator IM/PD1 logic module.
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items:
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- const: arm,pl180
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- const: arm,primecell
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- description: The improved version of the block, found in the
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ARM Versatile and later reference designs. Further revisions
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exist but get detected at runtime by reading some magic numbers
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in the PrimeCell ID registers.
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items:
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- const: arm,pl181
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- const: arm,primecell
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- description: Wildcard entry that will let the operating system
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inspect the PrimeCell ID registers to determine which hardware
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variant of PL180 or PL181 this is.
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items:
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- const: arm,pl18x
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- const: arm,primecell
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- description: Entries for STMicroelectronics variant of PL18x.
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items:
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- enum:
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- st,stm32-sdmmc2
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- st,stm32mp25-sdmmc2
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- const: arm,pl18x
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- const: arm,primecell
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clocks:
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description: One or two clocks, the "apb_pclk" and the "MCLK"
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which is the core block clock. The names are not compulsory.
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minItems: 1
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maxItems: 2
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dmas:
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maxItems: 2
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dma-names:
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oneOf:
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- items:
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- const: tx
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- const: rx
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- items:
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- const: rx
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- const: tx
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access-controllers:
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minItems: 1
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maxItems: 2
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power-domains: true
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resets:
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maxItems: 1
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reg:
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description: the MMIO memory window must be exactly 4KB (0x1000) and the
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layout should provide the PrimeCell ID registers so that the device can
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be discovered. On ST Micro variants, a second register window may be
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defined if a delay block is present and used for tuning.
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interrupts:
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description: The first interrupt is the command interrupt and corresponds
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to the event at the end of a command. The second interrupt is the
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PIO (polled I/O) interrupt and occurs when the FIFO needs to be
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emptied as part of a bulk read from the card. Some variants have these
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two interrupts wired into the same line (logic OR) and in that case
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only one interrupt may be provided. The interrupt-names property is
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not used due to inconsistency of existing DTs regarding its content.
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deprecated: false
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minItems: 1
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maxItems: 2
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st,sig-dir-dat0:
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$ref: /schemas/types.yaml#/definitions/flag
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description: ST Micro-specific property, bus signal direction pins used for
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DAT[0].
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st,sig-dir-dat2:
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$ref: /schemas/types.yaml#/definitions/flag
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description: ST Micro-specific property, bus signal direction pins used for
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DAT[2].
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st,sig-dir-dat31:
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$ref: /schemas/types.yaml#/definitions/flag
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description: ST Micro-specific property, bus signal direction pins used for
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DAT[3] and DAT[1].
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st,sig-dir-dat74:
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$ref: /schemas/types.yaml#/definitions/flag
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description: ST Micro-specific property, bus signal direction pins used for
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DAT[7] and DAT[4].
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st,sig-dir-cmd:
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$ref: /schemas/types.yaml#/definitions/flag
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description: ST Micro-specific property, CMD signal direction used for
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pin CMD.
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st,sig-pin-fbclk:
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$ref: /schemas/types.yaml#/definitions/flag
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description: ST Micro-specific property, feedback clock FBCLK signal pin
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in use.
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st,sig-dir:
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$ref: /schemas/types.yaml#/definitions/flag
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description: ST Micro-specific property, signal direction polarity used for
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pins CMD, DAT[0], DAT[1], DAT[2] and DAT[3].
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st,neg-edge:
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$ref: /schemas/types.yaml#/definitions/flag
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description: ST Micro-specific property, data and command phase relation,
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generated on the sd clock falling edge.
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st,use-ckin:
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$ref: /schemas/types.yaml#/definitions/flag
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description: ST Micro-specific property, use CKIN pin from an external
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driver to sample the receive data (for example with a voltage switch
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transceiver).
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st,cmd-gpios:
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maxItems: 1
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description:
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The GPIO matching the CMD pin.
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st,ck-gpios:
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maxItems: 1
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description:
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The GPIO matching the CK pin.
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st,ckin-gpios:
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maxItems: 1
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description:
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The GPIO matching the CKIN pin.
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dependencies:
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st,cmd-gpios: [ "st,use-ckin" ]
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st,ck-gpios: [ "st,use-ckin" ]
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st,ckin-gpios: [ "st,use-ckin" ]
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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mmc@5000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x5000 0x1000>;
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interrupts-extended = <&vic 22 &sic 1>;
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clocks = <&xtal24mhz>, <&pclk>;
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clock-names = "mclk", "apb_pclk";
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};
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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mmc@80126000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x80126000 0x1000>;
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interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma 29 0 0x2>, <&dma 29 0 0x0>;
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dma-names = "rx", "tx";
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clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
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clock-names = "sdi", "apb_pclk";
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max-frequency = <100000000>;
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bus-width = <4>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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cd-gpios = <&gpio2 31 0x4>;
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st,sig-dir-dat0;
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st,sig-dir-dat2;
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st,sig-dir-cmd;
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st,sig-pin-fbclk;
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vmmc-supply = <&ab8500_ldo_aux3_reg>;
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vqmmc-supply = <&vmmci>;
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};
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- |
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mmc@101f6000 {
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x101f6000 0x1000>;
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clocks = <&sdiclk>, <&pclksdi>;
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clock-names = "mclk", "apb_pclk";
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interrupts = <22>;
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max-frequency = <400000>;
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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full-pwr-cycle;
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st,sig-dir-dat0;
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st,sig-dir-dat2;
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st,sig-dir-dat31;
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st,sig-dir-cmd;
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st,sig-pin-fbclk;
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vmmc-supply = <&vmmc_regulator>;
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};
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- |
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mmc@52007000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x10153180>;
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reg = <0x52007000 0x1000>;
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interrupts = <49>;
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clocks = <&rcc 0>;
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clock-names = "apb_pclk";
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resets = <&rcc 1>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <120000000>;
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};
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