Masahiro Yamada 0316c018c5 clk: uniphier: add NAND 200MHz clock ...

The Denali NAND controller IP needs three clocks:

 - clk: controller core clock

 - clk_x: bus interface clock

 - ecc_clk: clock at which ECC circuitry is run

Currently, only the first one (50MHz) is provided.  The rest of the
two clock ports must be connected to the 200MHz clock line.  Add this.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

2018-07-25 15:45:25 -07:00

..

clk-uniphier-core.c

clk: uniphier: add PXs3 clock data

2017-08-31 18:34:35 -07:00

clk-uniphier-cpugear.c

clk: uniphier: remove unneeded #include <linux/delay.h>

2017-01-09 16:27:28 -08:00

clk-uniphier-fixed-factor.c

…

clk-uniphier-fixed-rate.c

…

clk-uniphier-gate.c

…

clk-uniphier-mio.c

clk: uniphier: fix parent of miodmac clock data

2017-11-14 10:04:04 -08:00

clk-uniphier-mux.c

clk: uniphier: fix type of variable passed to regmap_read()

2016-10-17 15:20:52 -07:00

clk-uniphier-peri.c

…

clk-uniphier-sys.c

clk: uniphier: add NAND 200MHz clock

2018-07-25 15:45:25 -07:00

clk-uniphier.h

clk: uniphier: add PXs3 clock data

2017-08-31 18:34:35 -07:00

Kconfig

…

Makefile

License cleanup: add SPDX GPL-2.0 license identifier to files with no license

2017-11-02 11:10:55 +01:00