Paul Cercueil 032f8c67fe drm/ingenic: Reset pixclock rate when parent clock rate changes ...

[ Upstream commit 33700f6f7d9f6b4e1e6df933ef7fd388889c662c ]

Old Ingenic SoCs can overclock very well, up to +50% of their nominal
clock rate, whithout requiring overvolting or anything like that, just
by changing the rate of the main PLL. Unfortunately, all clocks on the
system are derived from that PLL, and when the PLL rate is updated, so
is our pixel clock.

To counter that issue, we make sure that the panel is in VBLANK before
the rate change happens, and we will then re-set the pixel clock rate
afterwards, once the PLL has been changed, to be as close as possible to
the pixel rate requested by the encoder.

v2: Add comment about mutex usage

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20200926170501.1109197-2-paul@crapouillou.net
Signed-off-by: Sasha Levin <sashal@kernel.org>

2022-06-09 10:21:00 +02:00

..

drm

drm/ingenic: Reset pixclock rate when parent clock rate changes

2022-06-09 10:21:00 +02:00

host1x

gpu: host1x: Fix a memory leak in 'host1x_remove()'

2022-04-08 14:40:18 +02:00

ipu-v3

gpu: ipu-v3: Fix dev_dbg frequency output

2022-04-20 09:23:22 +02:00

trace

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vga

vgaarb: mark vga_tryget static

2020-08-01 11:28:17 +02:00

Makefile

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