3de9c42d02
NUMA enabled kernel on FDT based machine fails to boot because CPUs
are all in NUMA_NO_NODE and mm subsystem won't accept that.
Fix by adding them to default NUMA node at FDT parsing phase and move
numa_add_cpu(0) to a later point.
Cc: stable@vger.kernel.org
Fixes: 88d4d957ed
("LoongArch: Add FDT booting support from efi system table")
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
735 lines
16 KiB
C
735 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*
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* Derived from MIPS:
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* Copyright (C) 2000, 2001 Kanoj Sarcar
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* Copyright (C) 2000, 2001 Ralf Baechle
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* Copyright (C) 2000, 2001 Silicon Graphics, Inc.
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* Copyright (C) 2000, 2001, 2003 Broadcom Corporation
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*/
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#include <linux/acpi.h>
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#include <linux/cpu.h>
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#include <linux/cpumask.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/profile.h>
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#include <linux/seq_file.h>
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#include <linux/smp.h>
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#include <linux/threads.h>
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#include <linux/export.h>
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#include <linux/syscore_ops.h>
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#include <linux/time.h>
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#include <linux/tracepoint.h>
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#include <linux/sched/hotplug.h>
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#include <linux/sched/task_stack.h>
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#include <asm/cpu.h>
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#include <asm/idle.h>
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#include <asm/loongson.h>
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#include <asm/mmu_context.h>
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#include <asm/numa.h>
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#include <asm/paravirt.h>
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#include <asm/processor.h>
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#include <asm/setup.h>
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#include <asm/time.h>
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int __cpu_number_map[NR_CPUS]; /* Map physical to logical */
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EXPORT_SYMBOL(__cpu_number_map);
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int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */
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EXPORT_SYMBOL(__cpu_logical_map);
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/* Representing the threads (siblings) of each logical CPU */
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cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_sibling_map);
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/* Representing the core map of multi-core chips of each logical CPU */
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cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_core_map);
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static DECLARE_COMPLETION(cpu_starting);
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static DECLARE_COMPLETION(cpu_running);
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/*
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* A logcal cpu mask containing only one VPE per core to
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* reduce the number of IPIs on large MT systems.
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*/
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cpumask_t cpu_foreign_map[NR_CPUS] __read_mostly;
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EXPORT_SYMBOL(cpu_foreign_map);
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/* representing cpus for which sibling maps can be computed */
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static cpumask_t cpu_sibling_setup_map;
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/* representing cpus for which core maps can be computed */
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static cpumask_t cpu_core_setup_map;
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struct secondary_data cpuboot_data;
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static DEFINE_PER_CPU(int, cpu_state);
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static const char *ipi_types[NR_IPI] __tracepoint_string = {
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[IPI_RESCHEDULE] = "Rescheduling interrupts",
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[IPI_CALL_FUNCTION] = "Function call interrupts",
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};
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void show_ipi_list(struct seq_file *p, int prec)
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{
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unsigned int cpu, i;
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for (i = 0; i < NR_IPI; i++) {
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seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, prec >= 4 ? " " : "");
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for_each_online_cpu(cpu)
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seq_printf(p, "%10u ", per_cpu(irq_stat, cpu).ipi_irqs[i]);
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seq_printf(p, " LoongArch %d %s\n", i + 1, ipi_types[i]);
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}
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}
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static inline void set_cpu_core_map(int cpu)
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{
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int i;
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cpumask_set_cpu(cpu, &cpu_core_setup_map);
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for_each_cpu(i, &cpu_core_setup_map) {
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if (cpu_data[cpu].package == cpu_data[i].package) {
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cpumask_set_cpu(i, &cpu_core_map[cpu]);
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cpumask_set_cpu(cpu, &cpu_core_map[i]);
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}
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}
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}
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static inline void set_cpu_sibling_map(int cpu)
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{
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int i;
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cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
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for_each_cpu(i, &cpu_sibling_setup_map) {
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if (cpus_are_siblings(cpu, i)) {
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cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
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cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
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}
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}
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}
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static inline void clear_cpu_sibling_map(int cpu)
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{
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int i;
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for_each_cpu(i, &cpu_sibling_setup_map) {
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if (cpus_are_siblings(cpu, i)) {
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cpumask_clear_cpu(i, &cpu_sibling_map[cpu]);
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cpumask_clear_cpu(cpu, &cpu_sibling_map[i]);
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}
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}
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cpumask_clear_cpu(cpu, &cpu_sibling_setup_map);
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}
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/*
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* Calculate a new cpu_foreign_map mask whenever a
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* new cpu appears or disappears.
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*/
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void calculate_cpu_foreign_map(void)
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{
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int i, k, core_present;
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cpumask_t temp_foreign_map;
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/* Re-calculate the mask */
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cpumask_clear(&temp_foreign_map);
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for_each_online_cpu(i) {
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core_present = 0;
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for_each_cpu(k, &temp_foreign_map)
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if (cpus_are_siblings(i, k))
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core_present = 1;
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if (!core_present)
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cpumask_set_cpu(i, &temp_foreign_map);
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}
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for_each_online_cpu(i)
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cpumask_andnot(&cpu_foreign_map[i],
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&temp_foreign_map, &cpu_sibling_map[i]);
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}
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/* Send mailbox buffer via Mail_Send */
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static void csr_mail_send(uint64_t data, int cpu, int mailbox)
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{
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uint64_t val;
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/* Send high 32 bits */
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val = IOCSR_MBUF_SEND_BLOCKING;
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val |= (IOCSR_MBUF_SEND_BOX_HI(mailbox) << IOCSR_MBUF_SEND_BOX_SHIFT);
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val |= (cpu << IOCSR_MBUF_SEND_CPU_SHIFT);
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val |= (data & IOCSR_MBUF_SEND_H32_MASK);
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iocsr_write64(val, LOONGARCH_IOCSR_MBUF_SEND);
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/* Send low 32 bits */
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val = IOCSR_MBUF_SEND_BLOCKING;
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val |= (IOCSR_MBUF_SEND_BOX_LO(mailbox) << IOCSR_MBUF_SEND_BOX_SHIFT);
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val |= (cpu << IOCSR_MBUF_SEND_CPU_SHIFT);
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val |= (data << IOCSR_MBUF_SEND_BUF_SHIFT);
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iocsr_write64(val, LOONGARCH_IOCSR_MBUF_SEND);
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};
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static u32 ipi_read_clear(int cpu)
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{
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u32 action;
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/* Load the ipi register to figure out what we're supposed to do */
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action = iocsr_read32(LOONGARCH_IOCSR_IPI_STATUS);
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/* Clear the ipi register to clear the interrupt */
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iocsr_write32(action, LOONGARCH_IOCSR_IPI_CLEAR);
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wbflush();
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return action;
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}
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static void ipi_write_action(int cpu, u32 action)
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{
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uint32_t val;
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val = IOCSR_IPI_SEND_BLOCKING | action;
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val |= (cpu << IOCSR_IPI_SEND_CPU_SHIFT);
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iocsr_write32(val, LOONGARCH_IOCSR_IPI_SEND);
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}
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static void loongson_send_ipi_single(int cpu, unsigned int action)
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{
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ipi_write_action(cpu_logical_map(cpu), (u32)action);
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}
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static void loongson_send_ipi_mask(const struct cpumask *mask, unsigned int action)
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{
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unsigned int i;
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for_each_cpu(i, mask)
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ipi_write_action(cpu_logical_map(i), (u32)action);
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}
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/*
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* This function sends a 'reschedule' IPI to another CPU.
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* it goes straight through and wastes no time serializing
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* anything. Worst case is that we lose a reschedule ...
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*/
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void arch_smp_send_reschedule(int cpu)
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{
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mp_ops.send_ipi_single(cpu, ACTION_RESCHEDULE);
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}
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EXPORT_SYMBOL_GPL(arch_smp_send_reschedule);
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static irqreturn_t loongson_ipi_interrupt(int irq, void *dev)
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{
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unsigned int action;
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unsigned int cpu = smp_processor_id();
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action = ipi_read_clear(cpu_logical_map(cpu));
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if (action & SMP_RESCHEDULE) {
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scheduler_ipi();
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per_cpu(irq_stat, cpu).ipi_irqs[IPI_RESCHEDULE]++;
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}
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if (action & SMP_CALL_FUNCTION) {
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generic_smp_call_function_interrupt();
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per_cpu(irq_stat, cpu).ipi_irqs[IPI_CALL_FUNCTION]++;
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}
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return IRQ_HANDLED;
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}
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static void loongson_init_ipi(void)
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{
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int r, ipi_irq;
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ipi_irq = get_percpu_irq(INT_IPI);
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if (ipi_irq < 0)
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panic("IPI IRQ mapping failed\n");
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irq_set_percpu_devid(ipi_irq);
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r = request_percpu_irq(ipi_irq, loongson_ipi_interrupt, "IPI", &irq_stat);
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if (r < 0)
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panic("IPI IRQ request failed\n");
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}
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struct smp_ops mp_ops = {
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.init_ipi = loongson_init_ipi,
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.send_ipi_single = loongson_send_ipi_single,
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.send_ipi_mask = loongson_send_ipi_mask,
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};
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static void __init fdt_smp_setup(void)
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{
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#ifdef CONFIG_OF
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unsigned int cpu, cpuid;
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struct device_node *node = NULL;
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for_each_of_cpu_node(node) {
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if (!of_device_is_available(node))
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continue;
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cpuid = of_get_cpu_hwid(node, 0);
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if (cpuid >= nr_cpu_ids)
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continue;
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if (cpuid == loongson_sysconf.boot_cpu_id) {
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cpu = 0;
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} else {
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cpu = cpumask_next_zero(-1, cpu_present_mask);
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}
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num_processors++;
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set_cpu_possible(cpu, true);
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set_cpu_present(cpu, true);
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__cpu_number_map[cpuid] = cpu;
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__cpu_logical_map[cpu] = cpuid;
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early_numa_add_cpu(cpu, 0);
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set_cpuid_to_node(cpuid, 0);
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}
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loongson_sysconf.nr_cpus = num_processors;
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set_bit(0, loongson_sysconf.cores_io_master);
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#endif
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}
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void __init loongson_smp_setup(void)
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{
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fdt_smp_setup();
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if (loongson_sysconf.cores_per_package == 0)
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loongson_sysconf.cores_per_package = num_processors;
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cpu_data[0].core = cpu_logical_map(0) % loongson_sysconf.cores_per_package;
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cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
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pv_ipi_init();
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iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_EN);
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pr_info("Detected %i available CPU(s)\n", loongson_sysconf.nr_cpus);
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}
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void __init loongson_prepare_cpus(unsigned int max_cpus)
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{
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int i = 0;
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parse_acpi_topology();
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for (i = 0; i < loongson_sysconf.nr_cpus; i++) {
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set_cpu_present(i, true);
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csr_mail_send(0, __cpu_logical_map[i], 0);
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cpu_data[i].global_id = __cpu_logical_map[i];
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}
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per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
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}
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/*
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* Setup the PC, SP, and TP of a secondary processor and start it running!
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*/
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void loongson_boot_secondary(int cpu, struct task_struct *idle)
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{
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unsigned long entry;
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pr_info("Booting CPU#%d...\n", cpu);
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entry = __pa_symbol((unsigned long)&smpboot_entry);
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cpuboot_data.stack = (unsigned long)__KSTK_TOS(idle);
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cpuboot_data.thread_info = (unsigned long)task_thread_info(idle);
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csr_mail_send(entry, cpu_logical_map(cpu), 0);
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loongson_send_ipi_single(cpu, ACTION_BOOT_CPU);
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}
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/*
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* SMP init and finish on secondary CPUs
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*/
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void loongson_init_secondary(void)
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{
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unsigned int cpu = smp_processor_id();
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unsigned int imask = ECFGF_IP0 | ECFGF_IP1 | ECFGF_IP2 |
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ECFGF_IPI | ECFGF_PMC | ECFGF_TIMER | ECFGF_SIP0;
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change_csr_ecfg(ECFG0_IM, imask);
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iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_EN);
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#ifdef CONFIG_NUMA
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numa_add_cpu(cpu);
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#endif
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per_cpu(cpu_state, cpu) = CPU_ONLINE;
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cpu_data[cpu].package =
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cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;
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cpu_data[cpu].core = pptt_enabled ? cpu_data[cpu].core :
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cpu_logical_map(cpu) % loongson_sysconf.cores_per_package;
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}
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void loongson_smp_finish(void)
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{
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local_irq_enable();
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iocsr_write64(0, LOONGARCH_IOCSR_MBUF0);
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pr_info("CPU#%d finished\n", smp_processor_id());
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}
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#ifdef CONFIG_HOTPLUG_CPU
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int loongson_cpu_disable(void)
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{
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unsigned long flags;
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unsigned int cpu = smp_processor_id();
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if (io_master(cpu))
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return -EBUSY;
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#ifdef CONFIG_NUMA
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numa_remove_cpu(cpu);
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#endif
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set_cpu_online(cpu, false);
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clear_cpu_sibling_map(cpu);
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calculate_cpu_foreign_map();
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local_irq_save(flags);
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irq_migrate_all_off_this_cpu();
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clear_csr_ecfg(ECFG0_IM);
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local_irq_restore(flags);
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local_flush_tlb_all();
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return 0;
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}
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void loongson_cpu_die(unsigned int cpu)
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{
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while (per_cpu(cpu_state, cpu) != CPU_DEAD)
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cpu_relax();
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mb();
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}
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void __noreturn arch_cpu_idle_dead(void)
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{
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register uint64_t addr;
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register void (*init_fn)(void);
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idle_task_exit();
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local_irq_enable();
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set_csr_ecfg(ECFGF_IPI);
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__this_cpu_write(cpu_state, CPU_DEAD);
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__smp_mb();
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do {
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__asm__ __volatile__("idle 0\n\t");
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addr = iocsr_read64(LOONGARCH_IOCSR_MBUF0);
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} while (addr == 0);
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local_irq_disable();
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init_fn = (void *)TO_CACHE(addr);
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iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_CLEAR);
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init_fn();
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BUG();
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}
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#endif
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/*
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* Power management
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*/
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#ifdef CONFIG_PM
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static int loongson_ipi_suspend(void)
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{
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return 0;
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}
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static void loongson_ipi_resume(void)
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{
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iocsr_write32(0xffffffff, LOONGARCH_IOCSR_IPI_EN);
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}
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static struct syscore_ops loongson_ipi_syscore_ops = {
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.resume = loongson_ipi_resume,
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.suspend = loongson_ipi_suspend,
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};
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/*
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* Enable boot cpu ipi before enabling nonboot cpus
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* during syscore_resume.
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*/
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static int __init ipi_pm_init(void)
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{
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register_syscore_ops(&loongson_ipi_syscore_ops);
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return 0;
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}
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core_initcall(ipi_pm_init);
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#endif
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/* Preload SMP state for boot cpu */
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void smp_prepare_boot_cpu(void)
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{
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unsigned int cpu, node, rr_node;
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set_cpu_possible(0, true);
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set_cpu_online(0, true);
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set_my_cpu_offset(per_cpu_offset(0));
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numa_add_cpu(0);
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rr_node = first_node(node_online_map);
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for_each_possible_cpu(cpu) {
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node = early_cpu_to_node(cpu);
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/*
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* The mapping between present cpus and nodes has been
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* built during MADT and SRAT parsing.
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*
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* If possible cpus = present cpus here, early_cpu_to_node
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* will return valid node.
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*
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* If possible cpus > present cpus here (e.g. some possible
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* cpus will be added by cpu-hotplug later), for possible but
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* not present cpus, early_cpu_to_node will return NUMA_NO_NODE,
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* and we just map them to online nodes in round-robin way.
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* Once hotplugged, new correct mapping will be built for them.
|
|
*/
|
|
if (node != NUMA_NO_NODE)
|
|
set_cpu_numa_node(cpu, node);
|
|
else {
|
|
set_cpu_numa_node(cpu, rr_node);
|
|
rr_node = next_node_in(rr_node, node_online_map);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* called from main before smp_init() */
|
|
void __init smp_prepare_cpus(unsigned int max_cpus)
|
|
{
|
|
init_new_context(current, &init_mm);
|
|
current_thread_info()->cpu = 0;
|
|
loongson_prepare_cpus(max_cpus);
|
|
set_cpu_sibling_map(0);
|
|
set_cpu_core_map(0);
|
|
calculate_cpu_foreign_map();
|
|
#ifndef CONFIG_HOTPLUG_CPU
|
|
init_cpu_present(cpu_possible_mask);
|
|
#endif
|
|
}
|
|
|
|
int __cpu_up(unsigned int cpu, struct task_struct *tidle)
|
|
{
|
|
loongson_boot_secondary(cpu, tidle);
|
|
|
|
/* Wait for CPU to start and be ready to sync counters */
|
|
if (!wait_for_completion_timeout(&cpu_starting,
|
|
msecs_to_jiffies(5000))) {
|
|
pr_crit("CPU%u: failed to start\n", cpu);
|
|
return -EIO;
|
|
}
|
|
|
|
/* Wait for CPU to finish startup & mark itself online before return */
|
|
wait_for_completion(&cpu_running);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* First C code run on the secondary CPUs after being started up by
|
|
* the master.
|
|
*/
|
|
asmlinkage void start_secondary(void)
|
|
{
|
|
unsigned int cpu;
|
|
|
|
sync_counter();
|
|
cpu = raw_smp_processor_id();
|
|
set_my_cpu_offset(per_cpu_offset(cpu));
|
|
|
|
cpu_probe();
|
|
constant_clockevent_init();
|
|
loongson_init_secondary();
|
|
|
|
set_cpu_sibling_map(cpu);
|
|
set_cpu_core_map(cpu);
|
|
|
|
notify_cpu_starting(cpu);
|
|
|
|
/* Notify boot CPU that we're starting */
|
|
complete(&cpu_starting);
|
|
|
|
/* The CPU is running, now mark it online */
|
|
set_cpu_online(cpu, true);
|
|
|
|
calculate_cpu_foreign_map();
|
|
|
|
/*
|
|
* Notify boot CPU that we're up & online and it can safely return
|
|
* from __cpu_up()
|
|
*/
|
|
complete(&cpu_running);
|
|
|
|
/*
|
|
* irq will be enabled in loongson_smp_finish(), enabling it too
|
|
* early is dangerous.
|
|
*/
|
|
WARN_ON_ONCE(!irqs_disabled());
|
|
loongson_smp_finish();
|
|
|
|
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
|
|
}
|
|
|
|
void __init smp_cpus_done(unsigned int max_cpus)
|
|
{
|
|
}
|
|
|
|
static void stop_this_cpu(void *dummy)
|
|
{
|
|
set_cpu_online(smp_processor_id(), false);
|
|
calculate_cpu_foreign_map();
|
|
local_irq_disable();
|
|
while (true);
|
|
}
|
|
|
|
void smp_send_stop(void)
|
|
{
|
|
smp_call_function(stop_this_cpu, NULL, 0);
|
|
}
|
|
|
|
#ifdef CONFIG_PROFILING
|
|
int setup_profiling_timer(unsigned int multiplier)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static void flush_tlb_all_ipi(void *info)
|
|
{
|
|
local_flush_tlb_all();
|
|
}
|
|
|
|
void flush_tlb_all(void)
|
|
{
|
|
on_each_cpu(flush_tlb_all_ipi, NULL, 1);
|
|
}
|
|
|
|
static void flush_tlb_mm_ipi(void *mm)
|
|
{
|
|
local_flush_tlb_mm((struct mm_struct *)mm);
|
|
}
|
|
|
|
void flush_tlb_mm(struct mm_struct *mm)
|
|
{
|
|
if (atomic_read(&mm->mm_users) == 0)
|
|
return; /* happens as a result of exit_mmap() */
|
|
|
|
preempt_disable();
|
|
|
|
if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
|
|
on_each_cpu_mask(mm_cpumask(mm), flush_tlb_mm_ipi, mm, 1);
|
|
} else {
|
|
unsigned int cpu;
|
|
|
|
for_each_online_cpu(cpu) {
|
|
if (cpu != smp_processor_id() && cpu_context(cpu, mm))
|
|
cpu_context(cpu, mm) = 0;
|
|
}
|
|
local_flush_tlb_mm(mm);
|
|
}
|
|
|
|
preempt_enable();
|
|
}
|
|
|
|
struct flush_tlb_data {
|
|
struct vm_area_struct *vma;
|
|
unsigned long addr1;
|
|
unsigned long addr2;
|
|
};
|
|
|
|
static void flush_tlb_range_ipi(void *info)
|
|
{
|
|
struct flush_tlb_data *fd = info;
|
|
|
|
local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
|
|
}
|
|
|
|
void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
|
|
{
|
|
struct mm_struct *mm = vma->vm_mm;
|
|
|
|
preempt_disable();
|
|
if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
|
|
struct flush_tlb_data fd = {
|
|
.vma = vma,
|
|
.addr1 = start,
|
|
.addr2 = end,
|
|
};
|
|
|
|
on_each_cpu_mask(mm_cpumask(mm), flush_tlb_range_ipi, &fd, 1);
|
|
} else {
|
|
unsigned int cpu;
|
|
|
|
for_each_online_cpu(cpu) {
|
|
if (cpu != smp_processor_id() && cpu_context(cpu, mm))
|
|
cpu_context(cpu, mm) = 0;
|
|
}
|
|
local_flush_tlb_range(vma, start, end);
|
|
}
|
|
preempt_enable();
|
|
}
|
|
|
|
static void flush_tlb_kernel_range_ipi(void *info)
|
|
{
|
|
struct flush_tlb_data *fd = info;
|
|
|
|
local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
|
|
}
|
|
|
|
void flush_tlb_kernel_range(unsigned long start, unsigned long end)
|
|
{
|
|
struct flush_tlb_data fd = {
|
|
.addr1 = start,
|
|
.addr2 = end,
|
|
};
|
|
|
|
on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1);
|
|
}
|
|
|
|
static void flush_tlb_page_ipi(void *info)
|
|
{
|
|
struct flush_tlb_data *fd = info;
|
|
|
|
local_flush_tlb_page(fd->vma, fd->addr1);
|
|
}
|
|
|
|
void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
|
|
{
|
|
preempt_disable();
|
|
if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
|
|
struct flush_tlb_data fd = {
|
|
.vma = vma,
|
|
.addr1 = page,
|
|
};
|
|
|
|
on_each_cpu_mask(mm_cpumask(vma->vm_mm), flush_tlb_page_ipi, &fd, 1);
|
|
} else {
|
|
unsigned int cpu;
|
|
|
|
for_each_online_cpu(cpu) {
|
|
if (cpu != smp_processor_id() && cpu_context(cpu, vma->vm_mm))
|
|
cpu_context(cpu, vma->vm_mm) = 0;
|
|
}
|
|
local_flush_tlb_page(vma, page);
|
|
}
|
|
preempt_enable();
|
|
}
|
|
EXPORT_SYMBOL(flush_tlb_page);
|
|
|
|
static void flush_tlb_one_ipi(void *info)
|
|
{
|
|
unsigned long vaddr = (unsigned long) info;
|
|
|
|
local_flush_tlb_one(vaddr);
|
|
}
|
|
|
|
void flush_tlb_one(unsigned long vaddr)
|
|
{
|
|
on_each_cpu(flush_tlb_one_ipi, (void *)vaddr, 1);
|
|
}
|
|
EXPORT_SYMBOL(flush_tlb_one);
|