a6bbf5d4d9
Add the required types and descriptor accessors to support 5 levels of paging in the common code. This is one of the prerequisites for supporting 52-bit virtual addressing with 4k pages. Note that this does not cover the code that handles kernel mappings or the fixmap. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20240214122845.2033971-76-ardb+git@google.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
66 lines
1.3 KiB
C
66 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* PGD allocation/freeing
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*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*/
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#include <linux/mm.h>
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#include <linux/gfp.h>
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#include <linux/highmem.h>
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#include <linux/slab.h>
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#include <asm/pgalloc.h>
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#include <asm/page.h>
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#include <asm/tlbflush.h>
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static struct kmem_cache *pgd_cache __ro_after_init;
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static bool pgdir_is_page_size(void)
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{
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if (PGD_SIZE == PAGE_SIZE)
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return true;
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if (CONFIG_PGTABLE_LEVELS == 5)
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return !pgtable_l5_enabled();
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return false;
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}
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pgd_t *pgd_alloc(struct mm_struct *mm)
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{
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gfp_t gfp = GFP_PGTABLE_USER;
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if (pgdir_is_page_size())
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return (pgd_t *)__get_free_page(gfp);
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else
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return kmem_cache_alloc(pgd_cache, gfp);
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}
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void pgd_free(struct mm_struct *mm, pgd_t *pgd)
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{
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if (pgdir_is_page_size())
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free_page((unsigned long)pgd);
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else
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kmem_cache_free(pgd_cache, pgd);
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}
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void __init pgtable_cache_init(void)
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{
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if (pgdir_is_page_size())
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return;
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#ifdef CONFIG_ARM64_PA_BITS_52
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/*
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* With 52-bit physical addresses, the architecture requires the
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* top-level table to be aligned to at least 64 bytes.
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*/
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BUILD_BUG_ON(PGD_SIZE < 64);
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#endif
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/*
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* Naturally aligned pgds required by the architecture.
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*/
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pgd_cache = kmem_cache_create("pgd_cache", PGD_SIZE, PGD_SIZE,
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SLAB_PANIC, NULL);
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}
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