f3e893626a
The VSC7512 is a networking chip that contains several peripherals. Many of these peripherals are currently supported by the VSC7513 and VSC7514 chips, but those run on an internal CPU. The VSC7512 lacks this CPU, and must be controlled externally. Utilize the existing drivers by referencing the chip as an MFD. Add support for the two MDIO buses, the internal phys, pinctrl, and serial GPIO. Signed-off-by: Colin Foster <colin.foster@in-advantage.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20220905162132.2943088-9-colin.foster@in-advantage.com
162 lines
4.5 KiB
C
162 lines
4.5 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Core driver for the Ocelot chip family.
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*
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* The VSC7511, 7512, 7513, and 7514 can be controlled internally via an
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* on-chip MIPS processor, or externally via SPI, I2C, PCIe. This core driver is
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* intended to be the bus-agnostic glue between, for example, the SPI bus and
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* the child devices.
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*
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* Copyright 2021-2022 Innovative Advantage Inc.
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*
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* Author: Colin Foster <colin.foster@in-advantage.com>
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*/
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#include <linux/bits.h>
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#include <linux/device.h>
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#include <linux/export.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/ocelot.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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#include <linux/types.h>
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#include <soc/mscc/ocelot.h>
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#include "ocelot.h"
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#define REG_GCB_SOFT_RST 0x0008
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#define BIT_SOFT_CHIP_RST BIT(0)
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#define VSC7512_MIIM0_RES_START 0x7107009c
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#define VSC7512_MIIM1_RES_START 0x710700c0
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#define VSC7512_MIIM_RES_SIZE 0x024
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#define VSC7512_PHY_RES_START 0x710700f0
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#define VSC7512_PHY_RES_SIZE 0x004
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#define VSC7512_GPIO_RES_START 0x71070034
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#define VSC7512_GPIO_RES_SIZE 0x06c
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#define VSC7512_SIO_CTRL_RES_START 0x710700f8
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#define VSC7512_SIO_CTRL_RES_SIZE 0x100
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#define VSC7512_GCB_RST_SLEEP_US 100
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#define VSC7512_GCB_RST_TIMEOUT_US 100000
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static int ocelot_gcb_chip_rst_status(struct ocelot_ddata *ddata)
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{
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int val, err;
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err = regmap_read(ddata->gcb_regmap, REG_GCB_SOFT_RST, &val);
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if (err)
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return err;
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return val;
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}
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int ocelot_chip_reset(struct device *dev)
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{
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struct ocelot_ddata *ddata = dev_get_drvdata(dev);
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int ret, val;
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/*
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* Reset the entire chip here to put it into a completely known state.
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* Other drivers may want to reset their own subsystems. The register
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* self-clears, so one write is all that is needed and wait for it to
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* clear.
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*/
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ret = regmap_write(ddata->gcb_regmap, REG_GCB_SOFT_RST, BIT_SOFT_CHIP_RST);
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if (ret)
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return ret;
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return readx_poll_timeout(ocelot_gcb_chip_rst_status, ddata, val, !val,
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VSC7512_GCB_RST_SLEEP_US, VSC7512_GCB_RST_TIMEOUT_US);
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}
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EXPORT_SYMBOL_NS(ocelot_chip_reset, MFD_OCELOT);
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static const struct resource vsc7512_miim0_resources[] = {
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DEFINE_RES_REG_NAMED(VSC7512_MIIM0_RES_START, VSC7512_MIIM_RES_SIZE, "gcb_miim0"),
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DEFINE_RES_REG_NAMED(VSC7512_PHY_RES_START, VSC7512_PHY_RES_SIZE, "gcb_phy"),
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};
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static const struct resource vsc7512_miim1_resources[] = {
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DEFINE_RES_REG_NAMED(VSC7512_MIIM1_RES_START, VSC7512_MIIM_RES_SIZE, "gcb_miim1"),
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};
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static const struct resource vsc7512_pinctrl_resources[] = {
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DEFINE_RES_REG_NAMED(VSC7512_GPIO_RES_START, VSC7512_GPIO_RES_SIZE, "gcb_gpio"),
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};
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static const struct resource vsc7512_sgpio_resources[] = {
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DEFINE_RES_REG_NAMED(VSC7512_SIO_CTRL_RES_START, VSC7512_SIO_CTRL_RES_SIZE, "gcb_sio"),
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};
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static const struct mfd_cell vsc7512_devs[] = {
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{
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.name = "ocelot-pinctrl",
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.of_compatible = "mscc,ocelot-pinctrl",
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.num_resources = ARRAY_SIZE(vsc7512_pinctrl_resources),
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.resources = vsc7512_pinctrl_resources,
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}, {
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.name = "ocelot-sgpio",
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.of_compatible = "mscc,ocelot-sgpio",
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.num_resources = ARRAY_SIZE(vsc7512_sgpio_resources),
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.resources = vsc7512_sgpio_resources,
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}, {
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.name = "ocelot-miim0",
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.of_compatible = "mscc,ocelot-miim",
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.of_reg = VSC7512_MIIM0_RES_START,
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.use_of_reg = true,
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.num_resources = ARRAY_SIZE(vsc7512_miim0_resources),
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.resources = vsc7512_miim0_resources,
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}, {
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.name = "ocelot-miim1",
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.of_compatible = "mscc,ocelot-miim",
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.of_reg = VSC7512_MIIM1_RES_START,
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.use_of_reg = true,
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.num_resources = ARRAY_SIZE(vsc7512_miim1_resources),
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.resources = vsc7512_miim1_resources,
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},
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};
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static void ocelot_core_try_add_regmap(struct device *dev,
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const struct resource *res)
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{
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if (dev_get_regmap(dev, res->name))
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return;
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ocelot_spi_init_regmap(dev, res);
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}
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static void ocelot_core_try_add_regmaps(struct device *dev,
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const struct mfd_cell *cell)
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{
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int i;
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for (i = 0; i < cell->num_resources; i++)
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ocelot_core_try_add_regmap(dev, &cell->resources[i]);
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}
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int ocelot_core_init(struct device *dev)
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{
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int i, ndevs;
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ndevs = ARRAY_SIZE(vsc7512_devs);
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for (i = 0; i < ndevs; i++)
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ocelot_core_try_add_regmaps(dev, &vsc7512_devs[i]);
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return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, vsc7512_devs, ndevs, NULL, 0, NULL);
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}
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EXPORT_SYMBOL_NS(ocelot_core_init, MFD_OCELOT);
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MODULE_DESCRIPTION("Externally Controlled Ocelot Chip Driver");
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MODULE_AUTHOR("Colin Foster <colin.foster@in-advantage.com>");
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MODULE_LICENSE("GPL");
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MODULE_IMPORT_NS(MFD_OCELOT_SPI);
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