linux/drivers/pinctrl/intel
Mika Westerberg 03c4749dd6 gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation
We added acpi_gpiochip_pin_to_gpio_offset() because there was a need to
translate from ACPI GpioIo/GpioInt number to Linux GPIO number in the
Cherryview pinctrl driver. This translation is necessary because
Cherryview has gaps in the pin list and the driver used continuous GPIO
number space in Linux side as follows:

  created GPIO range 0->7 ==> INT33FF:03 PIN 0->7
  created GPIO range 8->19 ==> INT33FF:03 PIN 15->26
  created GPIO range 20->25 ==> INT33FF:03 PIN 30->35
  created GPIO range 26->33 ==> INT33FF:03 PIN 45->52
  created GPIO range 34->43 ==> INT33FF:03 PIN 60->69
  created GPIO range 44->54 ==> INT33FF:03 PIN 75->85

For example when ACPI GpioInt resource refers to GPIO 81 (SDMMC3_CD_B)
we translate from pin 81 to the corresponding Linux GPIO number, which
is 50. This number is then used when the GPIO is accessed through gpiolib.

It turns out, this is not necessary at all. We can just pass 1:1 mapping
between Linux GPIO numbers and pin numbers (including gaps) and the
pinctrl core handles all the details automatically:

  created GPIO range 0->7 ==> INT33FF:03 PIN 0->7
  created GPIO range 15->26 ==> INT33FF:03 PIN 15->26
  created GPIO range 30->35 ==> INT33FF:03 PIN 30->35
  created GPIO range 45->52 ==> INT33FF:03 PIN 45->52
  created GPIO range 60->69 ==> INT33FF:03 PIN 60->69
  created GPIO range 75->85 ==> INT33FF:03 PIN 75->85

Here GPIO 81 is exactly same than the hardware pin 81 (SDMMC3_CD_B).

As an added bonus this simplifies both the ACPI GPIO core code and the
Cherryview pinctrl driver.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-11-29 13:41:46 +01:00
..
Kconfig pinctrl: intel: Add Intel Cedar Fork PCH pin controller support 2017-10-31 10:11:21 +01:00
Makefile This is the bulk of pin control changes for the v4.15 2017-11-16 10:57:11 -08:00
pinctrl-baytrail.c gpio: Move irq_valid_mask into struct gpio_irq_chip 2017-11-08 14:10:18 +01:00
pinctrl-broxton.c pinctrl: broxton: No need to take pointer of a pointer 2017-01-30 14:45:12 +01:00
pinctrl-cannonlake.c pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support 2017-08-22 15:41:25 +02:00
pinctrl-cedarfork.c pinctrl: intel: Add Intel Cedar Fork PCH pin controller support 2017-10-31 10:11:21 +01:00
pinctrl-cherryview.c gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation 2017-11-29 13:41:46 +01:00
pinctrl-denverton.c pinctrl: intel: Add Intel Denverton pin controller support 2017-08-14 15:01:59 +02:00
pinctrl-geminilake.c pinctrl: intel: Add Intel Gemini Lake pin controller support 2017-01-30 15:06:01 +01:00
pinctrl-intel.c Merge branch 'gpio-irqchip-rework' of /home/linus/linux-gpio into devel 2017-11-09 09:38:42 +01:00
pinctrl-intel.h pinctrl: intel: Make offset to interrupt status register configurable 2017-10-31 10:10:24 +01:00
pinctrl-lewisburg.c pinctrl: intel: Add Intel Lewisburg GPIO support 2017-08-22 15:42:19 +02:00
pinctrl-merrifield.c pinctrl: intel: merrifield: Introduce ACPI device table 2017-11-29 10:29:45 +01:00
pinctrl-sunrisepoint.c pinctrl: intel: Add support for variable size pad groups 2017-06-09 13:01:35 +02:00