04876c12c1
The first patch in a series to split UMR logic to a dedicated file. As a start, move the init and cleanup of UMR resources to umr.c. Link: https://lore.kernel.org/r/849e632dd1945a2534712a320cc5779f2149ba96.1649747695.git.leonro@nvidia.com Signed-off-by: Aharon Landau <aharonl@nvidia.com> Reviewed-by: Michael Guralnik <michaelgur@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
107 lines
2.2 KiB
C
107 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
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/* Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. */
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#include "mlx5_ib.h"
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#include "umr.h"
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enum {
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MAX_UMR_WR = 128,
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};
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static int mlx5r_umr_qp_rst2rts(struct mlx5_ib_dev *dev, struct ib_qp *qp)
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{
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struct ib_qp_attr attr = {};
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int ret;
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attr.qp_state = IB_QPS_INIT;
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attr.port_num = 1;
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ret = ib_modify_qp(qp, &attr,
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IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT);
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if (ret) {
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mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
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return ret;
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}
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memset(&attr, 0, sizeof(attr));
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attr.qp_state = IB_QPS_RTR;
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ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
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if (ret) {
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mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
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return ret;
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}
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memset(&attr, 0, sizeof(attr));
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attr.qp_state = IB_QPS_RTS;
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ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
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if (ret) {
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mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
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return ret;
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}
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return 0;
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}
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int mlx5r_umr_resource_init(struct mlx5_ib_dev *dev)
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{
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struct ib_qp_init_attr init_attr = {};
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struct ib_pd *pd;
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struct ib_cq *cq;
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struct ib_qp *qp;
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int ret;
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pd = ib_alloc_pd(&dev->ib_dev, 0);
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if (IS_ERR(pd)) {
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mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
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return PTR_ERR(pd);
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}
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cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
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if (IS_ERR(cq)) {
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mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
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ret = PTR_ERR(cq);
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goto destroy_pd;
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}
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init_attr.send_cq = cq;
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init_attr.recv_cq = cq;
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init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
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init_attr.cap.max_send_wr = MAX_UMR_WR;
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init_attr.cap.max_send_sge = 1;
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init_attr.qp_type = MLX5_IB_QPT_REG_UMR;
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init_attr.port_num = 1;
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qp = ib_create_qp(pd, &init_attr);
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if (IS_ERR(qp)) {
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mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
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ret = PTR_ERR(qp);
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goto destroy_cq;
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}
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ret = mlx5r_umr_qp_rst2rts(dev, qp);
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if (ret)
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goto destroy_qp;
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dev->umrc.qp = qp;
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dev->umrc.cq = cq;
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dev->umrc.pd = pd;
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sema_init(&dev->umrc.sem, MAX_UMR_WR);
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return 0;
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destroy_qp:
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ib_destroy_qp(qp);
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destroy_cq:
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ib_free_cq(cq);
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destroy_pd:
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ib_dealloc_pd(pd);
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return ret;
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}
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void mlx5r_umr_resource_cleanup(struct mlx5_ib_dev *dev)
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{
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ib_destroy_qp(dev->umrc.qp);
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ib_free_cq(dev->umrc.cq);
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ib_dealloc_pd(dev->umrc.pd);
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}
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