Chen Feng 04d112690d reset: hisilicon: document hisi-hi6220 reset controllers bindings ...

Add DT bindings documentation for hi6220 SoC reset controller.

Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>

2015-11-20 15:41:28 +01:00

..

altr,rst-mgr-a10.h

dt-bindings: Add reset manager offsets for Arria10

2015-08-09 21:58:33 -05:00

altr,rst-mgr.h

ARM: socfpga: dts: add reset-controller

2014-05-05 22:33:18 -05:00

hisi,hi6220-resets.h

reset: hisilicon: document hisi-hi6220 reset controllers bindings

2015-11-20 15:41:28 +01:00

qcom,gcc-apq8084.h

clk: qcom: Add APQ8084 Global Clock Controller support

2014-07-11 13:22:00 -07:00

qcom,gcc-ipq806x.h

clk: qcom: Add support for NSS/GMAC clocks and resets

2015-05-30 17:04:36 -07:00

qcom,gcc-msm8660.h

clk: qcom: Add support for MSM8660's global clock controller (GCC)

2014-01-16 12:01:05 -08:00

qcom,gcc-msm8916.h

dt-bindings: Add #defines for MSM8916 clocks and resets

2015-03-23 16:09:20 -07:00

qcom,gcc-msm8960.h

clk: qcom: Fully support apq8064 global clock control

2014-07-11 13:21:22 -07:00

qcom,gcc-msm8974.h

clk: qcom: Add support for MSM8974's global clock controller (GCC)

2014-01-16 12:01:04 -08:00

qcom,mmcc-apq8084.h

clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support

2014-07-15 16:38:57 -07:00

qcom,mmcc-msm8960.h

clk: qcom: Add support for APQ8064 multimedia clocks

2014-07-15 16:39:03 -07:00

qcom,mmcc-msm8974.h

clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)

2014-01-16 12:01:05 -08:00

stih407-resets.h

ARM: STi: Add DT defines for co-processor reset lines

2015-11-16 09:23:47 +01:00

stih415-resets.h

ARM: STi: DT: Move reset controller constants into common location

2015-08-03 13:13:44 +02:00

stih416-resets.h

ARM: STi: DT: Move reset controller constants into common location

2015-08-03 13:13:44 +02:00

tegra124-car.h

clk: tegra: Add DFLL DVCO reset control for Tegra124

2015-07-16 09:32:48 +02:00