e42edf9b9d
Transactional Memory was removed from the architecture in ISA v3.1. For threads running in P8/P9 compatibility mode on P10 a synthetic TM implementation is provided. In this implementation, tbegin. always sets cr0 eq meaning the abort handler is always called. This is not an issue as users of TM are expected to have a fallback non transactional way to make forward progress in the abort handler. The TEXASR indicates if a transaction failure is due to a synthetic implementation. Some of the TM self tests need a non-degenerate TM implementation for their testing to be meaningful so check for a synthetic implementation and skip the test if so. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210729041317.366612-2-jniethe5@gmail.com
102 lines
2.2 KiB
C
102 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Test context switching to see if the DSCR SPR is correctly preserved
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* when within a transaction.
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*
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* Note: We assume that the DSCR has been left at the default value (0)
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* for all CPUs.
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*
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* Method:
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*
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* Set a value into the DSCR.
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*
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* Start a transaction, and suspend it (*).
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*
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* Hard loop checking to see if the transaction has become doomed.
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*
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* Now that we *may* have been preempted, record the DSCR and TEXASR SPRS.
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*
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* If the abort was because of a context switch, check the DSCR value.
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* Otherwise, try again.
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*
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* (*) If the transaction is not suspended we can't see the problem because
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* the transaction abort handler will restore the DSCR to it's checkpointed
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* value before we regain control.
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*/
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#include <inttypes.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <assert.h>
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#include <asm/tm.h>
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#include "utils.h"
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#include "tm.h"
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#include "../pmu/lib.h"
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#define SPRN_DSCR 0x03
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int test_body(void)
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{
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uint64_t rv, dscr1 = 1, dscr2, texasr;
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SKIP_IF(!have_htm());
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SKIP_IF(htm_is_synthetic());
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printf("Check DSCR TM context switch: ");
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fflush(stdout);
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for (;;) {
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asm __volatile__ (
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/* set a known value into the DSCR */
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"ld 3, %[dscr1];"
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"mtspr %[sprn_dscr], 3;"
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"li %[rv], 1;"
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/* start and suspend a transaction */
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"tbegin.;"
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"beq 1f;"
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"tsuspend.;"
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/* hard loop until the transaction becomes doomed */
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"2: ;"
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"tcheck 0;"
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"bc 4, 0, 2b;"
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/* record DSCR and TEXASR */
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"mfspr 3, %[sprn_dscr];"
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"std 3, %[dscr2];"
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"mfspr 3, %[sprn_texasr];"
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"std 3, %[texasr];"
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"tresume.;"
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"tend.;"
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"li %[rv], 0;"
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"1: ;"
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: [rv]"=r"(rv), [dscr2]"=m"(dscr2), [texasr]"=m"(texasr)
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: [dscr1]"m"(dscr1)
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, [sprn_dscr]"i"(SPRN_DSCR), [sprn_texasr]"i"(SPRN_TEXASR)
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: "memory", "r3"
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);
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assert(rv); /* make sure the transaction aborted */
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if ((texasr >> 56) != TM_CAUSE_RESCHED) {
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continue;
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}
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if (dscr2 != dscr1) {
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printf(" FAIL\n");
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return 1;
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} else {
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printf(" OK\n");
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return 0;
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}
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}
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}
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static int tm_resched_dscr(void)
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{
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return eat_cpu(test_body);
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}
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int main(int argc, const char *argv[])
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{
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return test_harness(tm_resched_dscr, "tm_resched_dscr");
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}
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