e42edf9b9d
Transactional Memory was removed from the architecture in ISA v3.1. For threads running in P8/P9 compatibility mode on P10 a synthetic TM implementation is provided. In this implementation, tbegin. always sets cr0 eq meaning the abort handler is always called. This is not an issue as users of TM are expected to have a fallback non transactional way to make forward progress in the abort handler. The TEXASR indicates if a transaction failure is due to a synthetic implementation. Some of the TM self tests need a non-degenerate TM implementation for their testing to be meaningful so check for a synthetic implementation and skip the test if so. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210729041317.366612-2-jniethe5@gmail.com
145 lines
2.9 KiB
C
145 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright 2015, Michael Neuling, IBM Corp.
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*
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* Original: Michael Neuling 3/4/2014
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* Modified: Rashmica Gupta 8/12/2015
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*
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* Check if any of the Transaction Memory SPRs get corrupted.
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* - TFIAR - stores address of location of transaction failure
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* - TFHAR - stores address of software failure handler (if transaction
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* fails)
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* - TEXASR - lots of info about the transacion(s)
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*
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* (1) create more threads than cpus
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* (2) in each thread:
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* (a) set TFIAR and TFHAR a unique value
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* (b) loop for awhile, continually checking to see if
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* either register has been corrupted.
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*
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* (3) Loop:
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* (a) begin transaction
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* (b) abort transaction
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* (c) check TEXASR to see if FS has been corrupted
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*/
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#define _GNU_SOURCE
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <pthread.h>
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#include <string.h>
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#include "utils.h"
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#include "tm.h"
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int num_loops = 1000000;
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int passed = 1;
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void tfiar_tfhar(void *in)
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{
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unsigned long tfhar, tfhar_rd, tfiar, tfiar_rd;
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int i;
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/* TFIAR: Last bit has to be high so userspace can read register */
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tfiar = ((unsigned long)in) + 1;
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tfiar += 2;
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mtspr(SPRN_TFIAR, tfiar);
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/* TFHAR: Last two bits are reserved */
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tfhar = ((unsigned long)in);
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tfhar &= ~0x3UL;
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tfhar += 4;
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mtspr(SPRN_TFHAR, tfhar);
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for (i = 0; i < num_loops; i++) {
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tfhar_rd = mfspr(SPRN_TFHAR);
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tfiar_rd = mfspr(SPRN_TFIAR);
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if ( (tfhar != tfhar_rd) || (tfiar != tfiar_rd) ) {
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passed = 0;
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return;
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}
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}
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return;
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}
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void texasr(void *in)
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{
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unsigned long i;
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uint64_t result = 0;
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for (i = 0; i < num_loops; i++) {
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asm __volatile__(
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"tbegin.;"
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"beq 3f ;"
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"tabort. 0 ;"
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"tend.;"
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/* Abort handler */
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"3: ;"
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::: "memory");
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/* Check the TEXASR */
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result = mfspr(SPRN_TEXASR);
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if ((result & TEXASR_FS) == 0) {
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passed = 0;
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return;
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}
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}
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return;
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}
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int test_tmspr()
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{
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pthread_t *thread;
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int thread_num;
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unsigned long i;
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SKIP_IF(!have_htm());
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SKIP_IF(htm_is_synthetic());
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/* To cause some context switching */
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thread_num = 10 * sysconf(_SC_NPROCESSORS_ONLN);
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thread = malloc(thread_num * sizeof(pthread_t));
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if (thread == NULL)
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return EXIT_FAILURE;
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/* Test TFIAR and TFHAR */
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for (i = 0; i < thread_num; i += 2) {
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if (pthread_create(&thread[i], NULL, (void *)tfiar_tfhar,
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(void *)i))
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return EXIT_FAILURE;
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}
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/* Test TEXASR */
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for (i = 1; i < thread_num; i += 2) {
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if (pthread_create(&thread[i], NULL, (void *)texasr, (void *)i))
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return EXIT_FAILURE;
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}
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for (i = 0; i < thread_num; i++) {
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if (pthread_join(thread[i], NULL) != 0)
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return EXIT_FAILURE;
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}
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free(thread);
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if (passed)
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return 0;
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else
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return 1;
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}
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int main(int argc, char *argv[])
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{
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if (argc > 1) {
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if (strcmp(argv[1], "-h") == 0) {
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printf("Syntax:\t [<num loops>]\n");
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return 0;
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} else {
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num_loops = atoi(argv[1]);
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}
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}
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return test_harness(test_tmspr, "tm_tmspr");
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}
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