408d808893
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it was merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Link: https://lore.kernel.org/r/20230714174434.4054728-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
545 lines
15 KiB
C
545 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (c) 2022 Nuvoton Technology Corporation
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#include <linux/debugfs.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "edac_module.h"
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#define EDAC_MOD_NAME "npcm-edac"
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#define EDAC_MSG_SIZE 256
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/* chip serials */
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#define NPCM7XX_CHIP BIT(0)
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#define NPCM8XX_CHIP BIT(1)
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/* syndrome values */
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#define UE_SYNDROME 0x03
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/* error injection */
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#define ERROR_TYPE_CORRECTABLE 0
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#define ERROR_TYPE_UNCORRECTABLE 1
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#define ERROR_LOCATION_DATA 0
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#define ERROR_LOCATION_CHECKCODE 1
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#define ERROR_BIT_DATA_MAX 63
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#define ERROR_BIT_CHECKCODE_MAX 7
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static char data_synd[] = {
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0xf4, 0xf1, 0xec, 0xea, 0xe9, 0xe6, 0xe5, 0xe3,
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0xdc, 0xda, 0xd9, 0xd6, 0xd5, 0xd3, 0xce, 0xcb,
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0xb5, 0xb0, 0xad, 0xab, 0xa8, 0xa7, 0xa4, 0xa2,
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0x9d, 0x9b, 0x98, 0x97, 0x94, 0x92, 0x8f, 0x8a,
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0x75, 0x70, 0x6d, 0x6b, 0x68, 0x67, 0x64, 0x62,
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0x5e, 0x5b, 0x58, 0x57, 0x54, 0x52, 0x4f, 0x4a,
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0x34, 0x31, 0x2c, 0x2a, 0x29, 0x26, 0x25, 0x23,
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0x1c, 0x1a, 0x19, 0x16, 0x15, 0x13, 0x0e, 0x0b
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};
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static struct regmap *npcm_regmap;
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struct npcm_platform_data {
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/* chip serials */
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int chip;
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/* memory controller registers */
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u32 ctl_ecc_en;
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u32 ctl_int_status;
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u32 ctl_int_ack;
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u32 ctl_int_mask_master;
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u32 ctl_int_mask_ecc;
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u32 ctl_ce_addr_l;
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u32 ctl_ce_addr_h;
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u32 ctl_ce_data_l;
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u32 ctl_ce_data_h;
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u32 ctl_ce_synd;
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u32 ctl_ue_addr_l;
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u32 ctl_ue_addr_h;
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u32 ctl_ue_data_l;
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u32 ctl_ue_data_h;
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u32 ctl_ue_synd;
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u32 ctl_source_id;
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u32 ctl_controller_busy;
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u32 ctl_xor_check_bits;
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/* masks and shifts */
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u32 ecc_en_mask;
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u32 int_status_ce_mask;
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u32 int_status_ue_mask;
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u32 int_ack_ce_mask;
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u32 int_ack_ue_mask;
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u32 int_mask_master_non_ecc_mask;
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u32 int_mask_master_global_mask;
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u32 int_mask_ecc_non_event_mask;
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u32 ce_addr_h_mask;
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u32 ce_synd_mask;
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u32 ce_synd_shift;
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u32 ue_addr_h_mask;
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u32 ue_synd_mask;
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u32 ue_synd_shift;
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u32 source_id_ce_mask;
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u32 source_id_ce_shift;
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u32 source_id_ue_mask;
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u32 source_id_ue_shift;
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u32 controller_busy_mask;
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u32 xor_check_bits_mask;
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u32 xor_check_bits_shift;
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u32 writeback_en_mask;
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u32 fwc_mask;
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};
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struct priv_data {
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void __iomem *reg;
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char message[EDAC_MSG_SIZE];
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const struct npcm_platform_data *pdata;
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/* error injection */
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struct dentry *debugfs;
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u8 error_type;
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u8 location;
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u8 bit;
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};
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static void handle_ce(struct mem_ctl_info *mci)
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{
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struct priv_data *priv = mci->pvt_info;
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const struct npcm_platform_data *pdata;
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u32 val_h = 0, val_l, id, synd;
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u64 addr = 0, data = 0;
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pdata = priv->pdata;
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regmap_read(npcm_regmap, pdata->ctl_ce_addr_l, &val_l);
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if (pdata->chip == NPCM8XX_CHIP) {
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regmap_read(npcm_regmap, pdata->ctl_ce_addr_h, &val_h);
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val_h &= pdata->ce_addr_h_mask;
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}
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addr = ((addr | val_h) << 32) | val_l;
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regmap_read(npcm_regmap, pdata->ctl_ce_data_l, &val_l);
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if (pdata->chip == NPCM8XX_CHIP)
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regmap_read(npcm_regmap, pdata->ctl_ce_data_h, &val_h);
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data = ((data | val_h) << 32) | val_l;
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regmap_read(npcm_regmap, pdata->ctl_source_id, &id);
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id = (id & pdata->source_id_ce_mask) >> pdata->source_id_ce_shift;
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regmap_read(npcm_regmap, pdata->ctl_ce_synd, &synd);
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synd = (synd & pdata->ce_synd_mask) >> pdata->ce_synd_shift;
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snprintf(priv->message, EDAC_MSG_SIZE,
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"addr = 0x%llx, data = 0x%llx, id = 0x%x", addr, data, id);
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, addr >> PAGE_SHIFT,
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addr & ~PAGE_MASK, synd, 0, 0, -1, priv->message, "");
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}
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static void handle_ue(struct mem_ctl_info *mci)
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{
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struct priv_data *priv = mci->pvt_info;
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const struct npcm_platform_data *pdata;
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u32 val_h = 0, val_l, id, synd;
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u64 addr = 0, data = 0;
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pdata = priv->pdata;
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regmap_read(npcm_regmap, pdata->ctl_ue_addr_l, &val_l);
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if (pdata->chip == NPCM8XX_CHIP) {
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regmap_read(npcm_regmap, pdata->ctl_ue_addr_h, &val_h);
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val_h &= pdata->ue_addr_h_mask;
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}
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addr = ((addr | val_h) << 32) | val_l;
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regmap_read(npcm_regmap, pdata->ctl_ue_data_l, &val_l);
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if (pdata->chip == NPCM8XX_CHIP)
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regmap_read(npcm_regmap, pdata->ctl_ue_data_h, &val_h);
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data = ((data | val_h) << 32) | val_l;
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regmap_read(npcm_regmap, pdata->ctl_source_id, &id);
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id = (id & pdata->source_id_ue_mask) >> pdata->source_id_ue_shift;
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regmap_read(npcm_regmap, pdata->ctl_ue_synd, &synd);
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synd = (synd & pdata->ue_synd_mask) >> pdata->ue_synd_shift;
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snprintf(priv->message, EDAC_MSG_SIZE,
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"addr = 0x%llx, data = 0x%llx, id = 0x%x", addr, data, id);
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, addr >> PAGE_SHIFT,
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addr & ~PAGE_MASK, synd, 0, 0, -1, priv->message, "");
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}
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static irqreturn_t edac_ecc_isr(int irq, void *dev_id)
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{
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const struct npcm_platform_data *pdata;
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struct mem_ctl_info *mci = dev_id;
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u32 status;
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pdata = ((struct priv_data *)mci->pvt_info)->pdata;
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regmap_read(npcm_regmap, pdata->ctl_int_status, &status);
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if (status & pdata->int_status_ce_mask) {
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handle_ce(mci);
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/* acknowledge the CE interrupt */
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regmap_write(npcm_regmap, pdata->ctl_int_ack,
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pdata->int_ack_ce_mask);
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return IRQ_HANDLED;
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} else if (status & pdata->int_status_ue_mask) {
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handle_ue(mci);
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/* acknowledge the UE interrupt */
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regmap_write(npcm_regmap, pdata->ctl_int_ack,
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pdata->int_ack_ue_mask);
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return IRQ_HANDLED;
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}
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WARN_ON_ONCE(1);
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return IRQ_NONE;
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}
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static ssize_t force_ecc_error(struct file *file, const char __user *data,
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size_t count, loff_t *ppos)
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{
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struct device *dev = file->private_data;
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struct mem_ctl_info *mci = to_mci(dev);
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struct priv_data *priv = mci->pvt_info;
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const struct npcm_platform_data *pdata;
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u32 val, syndrome;
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int ret;
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pdata = priv->pdata;
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edac_printk(KERN_INFO, EDAC_MOD_NAME,
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"force an ECC error, type = %d, location = %d, bit = %d\n",
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priv->error_type, priv->location, priv->bit);
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/* ensure no pending writes */
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ret = regmap_read_poll_timeout(npcm_regmap, pdata->ctl_controller_busy,
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val, !(val & pdata->controller_busy_mask),
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1000, 10000);
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if (ret) {
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edac_printk(KERN_INFO, EDAC_MOD_NAME,
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"wait pending writes timeout\n");
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return count;
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}
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regmap_read(npcm_regmap, pdata->ctl_xor_check_bits, &val);
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val &= ~pdata->xor_check_bits_mask;
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/* write syndrome to XOR_CHECK_BITS */
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if (priv->error_type == ERROR_TYPE_CORRECTABLE) {
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if (priv->location == ERROR_LOCATION_DATA &&
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priv->bit > ERROR_BIT_DATA_MAX) {
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edac_printk(KERN_INFO, EDAC_MOD_NAME,
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"data bit should not exceed %d (%d)\n",
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ERROR_BIT_DATA_MAX, priv->bit);
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return count;
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}
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if (priv->location == ERROR_LOCATION_CHECKCODE &&
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priv->bit > ERROR_BIT_CHECKCODE_MAX) {
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edac_printk(KERN_INFO, EDAC_MOD_NAME,
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"checkcode bit should not exceed %d (%d)\n",
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ERROR_BIT_CHECKCODE_MAX, priv->bit);
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return count;
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}
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syndrome = priv->location ? 1 << priv->bit
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: data_synd[priv->bit];
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regmap_write(npcm_regmap, pdata->ctl_xor_check_bits,
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val | (syndrome << pdata->xor_check_bits_shift) |
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pdata->writeback_en_mask);
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} else if (priv->error_type == ERROR_TYPE_UNCORRECTABLE) {
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regmap_write(npcm_regmap, pdata->ctl_xor_check_bits,
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val | (UE_SYNDROME << pdata->xor_check_bits_shift));
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}
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/* force write check */
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regmap_update_bits(npcm_regmap, pdata->ctl_xor_check_bits,
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pdata->fwc_mask, pdata->fwc_mask);
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return count;
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}
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static const struct file_operations force_ecc_error_fops = {
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.open = simple_open,
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.write = force_ecc_error,
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.llseek = generic_file_llseek,
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};
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/*
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* Setup debugfs for error injection.
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*
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* Nodes:
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* error_type - 0: CE, 1: UE
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* location - 0: data, 1: checkcode
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* bit - 0 ~ 63 for data and 0 ~ 7 for checkcode
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* force_ecc_error - trigger
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*
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* Examples:
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* 1. Inject a correctable error (CE) at checkcode bit 7.
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* ~# echo 0 > /sys/kernel/debug/edac/npcm-edac/error_type
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* ~# echo 1 > /sys/kernel/debug/edac/npcm-edac/location
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* ~# echo 7 > /sys/kernel/debug/edac/npcm-edac/bit
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* ~# echo 1 > /sys/kernel/debug/edac/npcm-edac/force_ecc_error
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*
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* 2. Inject an uncorrectable error (UE).
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* ~# echo 1 > /sys/kernel/debug/edac/npcm-edac/error_type
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* ~# echo 1 > /sys/kernel/debug/edac/npcm-edac/force_ecc_error
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*/
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static void setup_debugfs(struct mem_ctl_info *mci)
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{
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struct priv_data *priv = mci->pvt_info;
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priv->debugfs = edac_debugfs_create_dir(mci->mod_name);
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if (!priv->debugfs)
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return;
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edac_debugfs_create_x8("error_type", 0644, priv->debugfs, &priv->error_type);
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edac_debugfs_create_x8("location", 0644, priv->debugfs, &priv->location);
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edac_debugfs_create_x8("bit", 0644, priv->debugfs, &priv->bit);
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edac_debugfs_create_file("force_ecc_error", 0200, priv->debugfs,
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&mci->dev, &force_ecc_error_fops);
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}
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static int setup_irq(struct mem_ctl_info *mci, struct platform_device *pdev)
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{
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const struct npcm_platform_data *pdata;
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int ret, irq;
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pdata = ((struct priv_data *)mci->pvt_info)->pdata;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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edac_printk(KERN_ERR, EDAC_MOD_NAME, "IRQ not defined in DTS\n");
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return irq;
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}
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ret = devm_request_irq(&pdev->dev, irq, edac_ecc_isr, 0,
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dev_name(&pdev->dev), mci);
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if (ret < 0) {
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edac_printk(KERN_ERR, EDAC_MOD_NAME, "failed to request IRQ\n");
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return ret;
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}
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/* enable the functional group of ECC and mask the others */
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regmap_write(npcm_regmap, pdata->ctl_int_mask_master,
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pdata->int_mask_master_non_ecc_mask);
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if (pdata->chip == NPCM8XX_CHIP)
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regmap_write(npcm_regmap, pdata->ctl_int_mask_ecc,
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pdata->int_mask_ecc_non_event_mask);
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return 0;
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}
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static const struct regmap_config npcm_regmap_cfg = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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};
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static int edac_probe(struct platform_device *pdev)
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{
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const struct npcm_platform_data *pdata;
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struct device *dev = &pdev->dev;
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struct edac_mc_layer layers[1];
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struct mem_ctl_info *mci;
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struct priv_data *priv;
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void __iomem *reg;
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u32 val;
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int rc;
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reg = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(reg))
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return PTR_ERR(reg);
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npcm_regmap = devm_regmap_init_mmio(dev, reg, &npcm_regmap_cfg);
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if (IS_ERR(npcm_regmap))
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return PTR_ERR(npcm_regmap);
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pdata = of_device_get_match_data(dev);
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if (!pdata)
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return -EINVAL;
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/* bail out if ECC is not enabled */
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regmap_read(npcm_regmap, pdata->ctl_ecc_en, &val);
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if (!(val & pdata->ecc_en_mask)) {
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edac_printk(KERN_ERR, EDAC_MOD_NAME, "ECC is not enabled\n");
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return -EPERM;
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}
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edac_op_state = EDAC_OPSTATE_INT;
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layers[0].type = EDAC_MC_LAYER_ALL_MEM;
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layers[0].size = 1;
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
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sizeof(struct priv_data));
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if (!mci)
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return -ENOMEM;
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mci->pdev = &pdev->dev;
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priv = mci->pvt_info;
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priv->reg = reg;
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priv->pdata = pdata;
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platform_set_drvdata(pdev, mci);
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mci->mtype_cap = MEM_FLAG_DDR4;
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mci->edac_ctl_cap = EDAC_FLAG_SECDED;
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mci->scrub_cap = SCRUB_FLAG_HW_SRC;
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mci->scrub_mode = SCRUB_HW_SRC;
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mci->edac_cap = EDAC_FLAG_SECDED;
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mci->ctl_name = "npcm_ddr_controller";
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mci->dev_name = dev_name(&pdev->dev);
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mci->mod_name = EDAC_MOD_NAME;
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mci->ctl_page_to_phys = NULL;
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rc = setup_irq(mci, pdev);
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if (rc)
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goto free_edac_mc;
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rc = edac_mc_add_mc(mci);
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if (rc)
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goto free_edac_mc;
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if (IS_ENABLED(CONFIG_EDAC_DEBUG) && pdata->chip == NPCM8XX_CHIP)
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setup_debugfs(mci);
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return rc;
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free_edac_mc:
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edac_mc_free(mci);
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return rc;
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}
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static int edac_remove(struct platform_device *pdev)
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{
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struct mem_ctl_info *mci = platform_get_drvdata(pdev);
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struct priv_data *priv = mci->pvt_info;
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const struct npcm_platform_data *pdata;
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pdata = priv->pdata;
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if (IS_ENABLED(CONFIG_EDAC_DEBUG) && pdata->chip == NPCM8XX_CHIP)
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edac_debugfs_remove_recursive(priv->debugfs);
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edac_mc_del_mc(&pdev->dev);
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edac_mc_free(mci);
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regmap_write(npcm_regmap, pdata->ctl_int_mask_master,
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pdata->int_mask_master_global_mask);
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regmap_update_bits(npcm_regmap, pdata->ctl_ecc_en, pdata->ecc_en_mask, 0);
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return 0;
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}
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static const struct npcm_platform_data npcm750_edac = {
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.chip = NPCM7XX_CHIP,
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/* memory controller registers */
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.ctl_ecc_en = 0x174,
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.ctl_int_status = 0x1d0,
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.ctl_int_ack = 0x1d4,
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.ctl_int_mask_master = 0x1d8,
|
|
.ctl_ce_addr_l = 0x188,
|
|
.ctl_ce_data_l = 0x190,
|
|
.ctl_ce_synd = 0x18c,
|
|
.ctl_ue_addr_l = 0x17c,
|
|
.ctl_ue_data_l = 0x184,
|
|
.ctl_ue_synd = 0x180,
|
|
.ctl_source_id = 0x194,
|
|
|
|
/* masks and shifts */
|
|
.ecc_en_mask = BIT(24),
|
|
.int_status_ce_mask = GENMASK(4, 3),
|
|
.int_status_ue_mask = GENMASK(6, 5),
|
|
.int_ack_ce_mask = GENMASK(4, 3),
|
|
.int_ack_ue_mask = GENMASK(6, 5),
|
|
.int_mask_master_non_ecc_mask = GENMASK(30, 7) | GENMASK(2, 0),
|
|
.int_mask_master_global_mask = BIT(31),
|
|
.ce_synd_mask = GENMASK(6, 0),
|
|
.ce_synd_shift = 0,
|
|
.ue_synd_mask = GENMASK(6, 0),
|
|
.ue_synd_shift = 0,
|
|
.source_id_ce_mask = GENMASK(29, 16),
|
|
.source_id_ce_shift = 16,
|
|
.source_id_ue_mask = GENMASK(13, 0),
|
|
.source_id_ue_shift = 0,
|
|
};
|
|
|
|
static const struct npcm_platform_data npcm845_edac = {
|
|
.chip = NPCM8XX_CHIP,
|
|
|
|
/* memory controller registers */
|
|
.ctl_ecc_en = 0x16c,
|
|
.ctl_int_status = 0x228,
|
|
.ctl_int_ack = 0x244,
|
|
.ctl_int_mask_master = 0x220,
|
|
.ctl_int_mask_ecc = 0x260,
|
|
.ctl_ce_addr_l = 0x18c,
|
|
.ctl_ce_addr_h = 0x190,
|
|
.ctl_ce_data_l = 0x194,
|
|
.ctl_ce_data_h = 0x198,
|
|
.ctl_ce_synd = 0x190,
|
|
.ctl_ue_addr_l = 0x17c,
|
|
.ctl_ue_addr_h = 0x180,
|
|
.ctl_ue_data_l = 0x184,
|
|
.ctl_ue_data_h = 0x188,
|
|
.ctl_ue_synd = 0x180,
|
|
.ctl_source_id = 0x19c,
|
|
.ctl_controller_busy = 0x20c,
|
|
.ctl_xor_check_bits = 0x174,
|
|
|
|
/* masks and shifts */
|
|
.ecc_en_mask = GENMASK(17, 16),
|
|
.int_status_ce_mask = GENMASK(1, 0),
|
|
.int_status_ue_mask = GENMASK(3, 2),
|
|
.int_ack_ce_mask = GENMASK(1, 0),
|
|
.int_ack_ue_mask = GENMASK(3, 2),
|
|
.int_mask_master_non_ecc_mask = GENMASK(30, 3) | GENMASK(1, 0),
|
|
.int_mask_master_global_mask = BIT(31),
|
|
.int_mask_ecc_non_event_mask = GENMASK(8, 4),
|
|
.ce_addr_h_mask = GENMASK(1, 0),
|
|
.ce_synd_mask = GENMASK(15, 8),
|
|
.ce_synd_shift = 8,
|
|
.ue_addr_h_mask = GENMASK(1, 0),
|
|
.ue_synd_mask = GENMASK(15, 8),
|
|
.ue_synd_shift = 8,
|
|
.source_id_ce_mask = GENMASK(29, 16),
|
|
.source_id_ce_shift = 16,
|
|
.source_id_ue_mask = GENMASK(13, 0),
|
|
.source_id_ue_shift = 0,
|
|
.controller_busy_mask = BIT(0),
|
|
.xor_check_bits_mask = GENMASK(23, 16),
|
|
.xor_check_bits_shift = 16,
|
|
.writeback_en_mask = BIT(24),
|
|
.fwc_mask = BIT(8),
|
|
};
|
|
|
|
static const struct of_device_id npcm_edac_of_match[] = {
|
|
{
|
|
.compatible = "nuvoton,npcm750-memory-controller",
|
|
.data = &npcm750_edac
|
|
},
|
|
{
|
|
.compatible = "nuvoton,npcm845-memory-controller",
|
|
.data = &npcm845_edac
|
|
},
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, npcm_edac_of_match);
|
|
|
|
static struct platform_driver npcm_edac_driver = {
|
|
.driver = {
|
|
.name = "npcm-edac",
|
|
.of_match_table = npcm_edac_of_match,
|
|
},
|
|
.probe = edac_probe,
|
|
.remove = edac_remove,
|
|
};
|
|
|
|
module_platform_driver(npcm_edac_driver);
|
|
|
|
MODULE_AUTHOR("Medad CChien <medadyoung@gmail.com>");
|
|
MODULE_AUTHOR("Marvin Lin <kflin@nuvoton.com>");
|
|
MODULE_DESCRIPTION("Nuvoton NPCM EDAC Driver");
|
|
MODULE_LICENSE("GPL");
|