28f3be5180
Introduce PLL clock controller for Amlogic A1 SoC family. The clock unit is an APB slave module that is designed for generating all of the internal and system clocks. The SoC uses an external 24MHz crystal; there are 4 internal PLLs: SYS_PLL/HIFI_PLL/USB_PLL/(FIXPLL), these PLLs generate 27 clock sources. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230523135351.19133-5-ddrokosov@sberdevices.ru Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
48 lines
1.4 KiB
C
48 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Amlogic A1 PLL Clock Controller internals
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*
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* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
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* Author: Jian Hu <jian.hu@amlogic.com>
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*
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* Copyright (c) 2023, SberDevices. All Rights Reserved.
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* Author: Dmitry Rokosov <ddrokosov@sberdevices.ru>
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*/
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#ifndef __A1_PLL_H
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#define __A1_PLL_H
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#include "clk-pll.h"
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/* PLL register offset */
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#define ANACTRL_FIXPLL_CTRL0 0x0
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#define ANACTRL_FIXPLL_CTRL1 0x4
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#define ANACTRL_FIXPLL_STS 0x14
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#define ANACTRL_HIFIPLL_CTRL0 0xc0
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#define ANACTRL_HIFIPLL_CTRL1 0xc4
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#define ANACTRL_HIFIPLL_CTRL2 0xc8
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#define ANACTRL_HIFIPLL_CTRL3 0xcc
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#define ANACTRL_HIFIPLL_CTRL4 0xd0
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#define ANACTRL_HIFIPLL_STS 0xd4
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/* include the CLKIDs that have been made part of the DT binding */
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#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
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/*
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* CLKID index values for internal clocks
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*
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* These indices are entirely contrived and do not map onto the hardware.
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* It has now been decided to expose everything by default in the DT header:
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* include/dt-bindings/clock/a1-pll-clkc.h. Only the clocks ids we don't want
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* to expose, such as the internal muxes and dividers of composite clocks,
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* will remain defined here.
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*/
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#define CLKID_FIXED_PLL_DCO 0
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#define CLKID_FCLK_DIV2_DIV 2
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#define CLKID_FCLK_DIV3_DIV 3
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#define CLKID_FCLK_DIV5_DIV 4
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#define CLKID_FCLK_DIV7_DIV 5
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#define NR_PLL_CLKS 11
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#endif /* __A1_PLL_H */
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