c8afaa1b0f
The only remaining consumer is new_inode, where it showed up in 2001 as
commit c37fa164f793 ("v2.4.9.9 -> v2.4.9.10") in a historical repo [1]
with a changelog which does not mention it.
Since then the line got only touched up to keep compiling.
While it may have been of benefit back in the day, it is guaranteed to
at best not get in the way in the multicore setting -- as the code
performs *a lot* of work between the prefetch and actual lock acquire,
any contention means the cacheline is already invalid by the time the
routine calls spin_lock(). It adds spurious traffic, for short.
On top of it prefetch is notoriously tricky to use for single-threaded
purposes, making it questionable from the get go.
As such, remove it.
I admit upfront I did not see value in benchmarking this change, but I
can do it if that is deemed appropriate.
Removal from new_inode and of the entire thing are in the same patch as
requested by Linus, so whatever weird looks can be directed at that guy.
Link: https://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git/commit/fs/inode.c?id=c37fa164f793735b32aa3f53154ff1a7659e6442 [1]
Signed-off-by: Mateusz Guzik <mjguzik@gmail.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
248 lines
7.2 KiB
C
248 lines
7.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* include/asm/processor.h
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*
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef __ASM_SPARC64_PROCESSOR_H
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#define __ASM_SPARC64_PROCESSOR_H
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#include <asm/asi.h>
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#include <asm/pstate.h>
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#include <asm/ptrace.h>
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#include <asm/page.h>
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/*
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* User lives in his very own context, and cannot reference us. Note
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* that TASK_SIZE is a misnomer, it really gives maximum user virtual
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* address that the kernel will allocate out.
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*
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* XXX No longer using virtual page tables, kill this upper limit...
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*/
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#define VA_BITS 44
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#ifndef __ASSEMBLY__
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#define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
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#else
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#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
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#endif
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#define TASK_SIZE_OF(tsk) \
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(test_tsk_thread_flag(tsk,TIF_32BIT) ? \
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(1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
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#define TASK_SIZE \
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(test_thread_flag(TIF_32BIT) ? \
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(1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
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#ifdef __KERNEL__
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#define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE)
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#define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL))
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#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
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STACK_TOP32 : STACK_TOP64)
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#define STACK_TOP_MAX STACK_TOP64
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#endif
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#ifndef __ASSEMBLY__
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/* The Sparc processor specific thread struct. */
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/* XXX This should die, everything can go into thread_info now. */
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struct thread_struct {
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#ifdef CONFIG_DEBUG_SPINLOCK
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/* How many spinlocks held by this thread.
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* Used with spin lock debugging to catch tasks
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* sleeping illegally with locks held.
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*/
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int smp_lock_count;
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unsigned int smp_lock_pc;
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#else
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int dummy; /* f'in gcc bug... */
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#endif
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};
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#endif /* !(__ASSEMBLY__) */
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#ifndef CONFIG_DEBUG_SPINLOCK
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#define INIT_THREAD { \
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0, \
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}
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#else /* CONFIG_DEBUG_SPINLOCK */
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#define INIT_THREAD { \
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/* smp_lock_count, smp_lock_pc, */ \
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0, 0, \
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}
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#endif /* !(CONFIG_DEBUG_SPINLOCK) */
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <asm/fpumacro.h>
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struct task_struct;
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/* On Uniprocessor, even in RMO processes see TSO semantics */
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#ifdef CONFIG_SMP
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#define TSTATE_INITIAL_MM TSTATE_TSO
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#else
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#define TSTATE_INITIAL_MM TSTATE_RMO
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#endif
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/* Do necessary setup to start up a newly executed thread. */
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#define start_thread(regs, pc, sp) \
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do { \
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unsigned long __asi = ASI_PNF; \
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regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (__asi << 24UL); \
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regs->tpc = ((pc & (~3)) - 4); \
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regs->tnpc = regs->tpc + 4; \
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regs->y = 0; \
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set_thread_wstate(1 << 3); \
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if (current_thread_info()->utraps) { \
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if (*(current_thread_info()->utraps) < 2) \
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kfree(current_thread_info()->utraps); \
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else \
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(*(current_thread_info()->utraps))--; \
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current_thread_info()->utraps = NULL; \
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} \
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__asm__ __volatile__( \
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"stx %%g0, [%0 + %2 + 0x00]\n\t" \
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"stx %%g0, [%0 + %2 + 0x08]\n\t" \
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"stx %%g0, [%0 + %2 + 0x10]\n\t" \
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"stx %%g0, [%0 + %2 + 0x18]\n\t" \
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"stx %%g0, [%0 + %2 + 0x20]\n\t" \
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"stx %%g0, [%0 + %2 + 0x28]\n\t" \
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"stx %%g0, [%0 + %2 + 0x30]\n\t" \
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"stx %%g0, [%0 + %2 + 0x38]\n\t" \
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"stx %%g0, [%0 + %2 + 0x40]\n\t" \
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"stx %%g0, [%0 + %2 + 0x48]\n\t" \
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"stx %%g0, [%0 + %2 + 0x50]\n\t" \
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"stx %%g0, [%0 + %2 + 0x58]\n\t" \
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"stx %%g0, [%0 + %2 + 0x60]\n\t" \
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"stx %%g0, [%0 + %2 + 0x68]\n\t" \
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"stx %1, [%0 + %2 + 0x70]\n\t" \
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"stx %%g0, [%0 + %2 + 0x78]\n\t" \
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"wrpr %%g0, (1 << 3), %%wstate\n\t" \
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: \
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: "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
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"i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
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fprs_write(0); \
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current_thread_info()->xfsr[0] = 0; \
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current_thread_info()->fpsaved[0] = 0; \
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regs->tstate &= ~TSTATE_PEF; \
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} while (0)
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#define start_thread32(regs, pc, sp) \
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do { \
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unsigned long __asi = ASI_PNF; \
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pc &= 0x00000000ffffffffUL; \
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sp &= 0x00000000ffffffffUL; \
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regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM) | (__asi << 24UL); \
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regs->tpc = ((pc & (~3)) - 4); \
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regs->tnpc = regs->tpc + 4; \
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regs->y = 0; \
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set_thread_wstate(2 << 3); \
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if (current_thread_info()->utraps) { \
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if (*(current_thread_info()->utraps) < 2) \
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kfree(current_thread_info()->utraps); \
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else \
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(*(current_thread_info()->utraps))--; \
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current_thread_info()->utraps = NULL; \
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} \
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__asm__ __volatile__( \
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"stx %%g0, [%0 + %2 + 0x00]\n\t" \
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"stx %%g0, [%0 + %2 + 0x08]\n\t" \
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"stx %%g0, [%0 + %2 + 0x10]\n\t" \
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"stx %%g0, [%0 + %2 + 0x18]\n\t" \
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"stx %%g0, [%0 + %2 + 0x20]\n\t" \
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"stx %%g0, [%0 + %2 + 0x28]\n\t" \
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"stx %%g0, [%0 + %2 + 0x30]\n\t" \
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"stx %%g0, [%0 + %2 + 0x38]\n\t" \
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"stx %%g0, [%0 + %2 + 0x40]\n\t" \
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"stx %%g0, [%0 + %2 + 0x48]\n\t" \
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"stx %%g0, [%0 + %2 + 0x50]\n\t" \
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"stx %%g0, [%0 + %2 + 0x58]\n\t" \
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"stx %%g0, [%0 + %2 + 0x60]\n\t" \
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"stx %%g0, [%0 + %2 + 0x68]\n\t" \
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"stx %1, [%0 + %2 + 0x70]\n\t" \
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"stx %%g0, [%0 + %2 + 0x78]\n\t" \
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"wrpr %%g0, (2 << 3), %%wstate\n\t" \
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: \
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: "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
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"i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
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fprs_write(0); \
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current_thread_info()->xfsr[0] = 0; \
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current_thread_info()->fpsaved[0] = 0; \
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regs->tstate &= ~TSTATE_PEF; \
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} while (0)
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unsigned long __get_wchan(struct task_struct *task);
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#define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
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#define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc)
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#define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP])
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/* Please see the commentary in asm/backoff.h for a description of
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* what these instructions are doing and how they have been chosen.
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* To make a long story short, we are trying to yield the current cpu
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* strand during busy loops.
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*/
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#ifdef BUILD_VDSO
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#define cpu_relax() asm volatile("\n99:\n\t" \
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"rd %%ccr, %%g0\n\t" \
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"rd %%ccr, %%g0\n\t" \
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"rd %%ccr, %%g0\n\t" \
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::: "memory")
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#else /* ! BUILD_VDSO */
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#define cpu_relax() asm volatile("\n99:\n\t" \
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"rd %%ccr, %%g0\n\t" \
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"rd %%ccr, %%g0\n\t" \
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"rd %%ccr, %%g0\n\t" \
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".section .pause_3insn_patch,\"ax\"\n\t"\
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".word 99b\n\t" \
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"wr %%g0, 128, %%asr27\n\t" \
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"nop\n\t" \
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"nop\n\t" \
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".previous" \
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::: "memory")
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#endif
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/* Prefetch support. This is tuned for UltraSPARC-III and later.
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* UltraSPARC-I will treat these as nops, and UltraSPARC-II has
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* a shallower prefetch queue than later chips.
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*/
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#define ARCH_HAS_PREFETCH
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#define ARCH_HAS_PREFETCHW
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static inline void prefetch(const void *x)
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{
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/* We do not use the read prefetch mnemonic because that
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* prefetches into the prefetch-cache which only is accessible
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* by floating point operations in UltraSPARC-III and later.
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* By contrast, "#one_write" prefetches into the L2 cache
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* in shared state.
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*/
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__asm__ __volatile__("prefetch [%0], #one_write"
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: /* no outputs */
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: "r" (x));
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}
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static inline void prefetchw(const void *x)
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{
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/* The most optimal prefetch to use for writes is
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* "#n_writes". This brings the cacheline into the
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* L2 cache in "owned" state.
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*/
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__asm__ __volatile__("prefetch [%0], #n_writes"
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: /* no outputs */
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: "r" (x));
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}
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#define HAVE_ARCH_PICK_MMAP_LAYOUT
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int do_mathemu(struct pt_regs *regs, struct fpustate *f, bool illegal_insn_trap);
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#endif /* !(__ASSEMBLY__) */
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#endif /* !(__ASM_SPARC64_PROCESSOR_H) */
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