4a20bc3e20
CXL is using tracepoints for reporting RAS capability register payloads for AER events, and has plans to use tracepoints for the output payload of Get Poison List and Get Event Records commands. For organization purposes it would be nice to keep those all under a single + local CXL trace system. This also organization also potentially helps in the future when CXL drivers expand beyond generic memory expanders, however that would also entail a move away from the expander-specific cxl_dev_state context, save that for later. Note that the powerpc-specific drivers/misc/cxl/ also defines a 'cxl' trace system, however, it is unlikely that a single platform will ever load both drivers simultaneously. Cc: Steven Rostedt <rostedt@goodmis.org> Tested-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/167051869176.436579.9728373544811641087.stgit@dwillia2-xfh.jf.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
110 lines
3.8 KiB
C
110 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
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#undef TRACE_SYSTEM
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#define TRACE_SYSTEM cxl
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#if !defined(_CXL_EVENTS_H) || defined(TRACE_HEADER_MULTI_READ)
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#define _CXL_EVENTS_H
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#include <cxl.h>
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#include <linux/tracepoint.h>
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#define CXL_RAS_UC_CACHE_DATA_PARITY BIT(0)
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#define CXL_RAS_UC_CACHE_ADDR_PARITY BIT(1)
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#define CXL_RAS_UC_CACHE_BE_PARITY BIT(2)
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#define CXL_RAS_UC_CACHE_DATA_ECC BIT(3)
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#define CXL_RAS_UC_MEM_DATA_PARITY BIT(4)
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#define CXL_RAS_UC_MEM_ADDR_PARITY BIT(5)
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#define CXL_RAS_UC_MEM_BE_PARITY BIT(6)
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#define CXL_RAS_UC_MEM_DATA_ECC BIT(7)
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#define CXL_RAS_UC_REINIT_THRESH BIT(8)
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#define CXL_RAS_UC_RSVD_ENCODE BIT(9)
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#define CXL_RAS_UC_POISON BIT(10)
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#define CXL_RAS_UC_RECV_OVERFLOW BIT(11)
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#define CXL_RAS_UC_INTERNAL_ERR BIT(14)
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#define CXL_RAS_UC_IDE_TX_ERR BIT(15)
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#define CXL_RAS_UC_IDE_RX_ERR BIT(16)
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#define show_uc_errs(status) __print_flags(status, " | ", \
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{ CXL_RAS_UC_CACHE_DATA_PARITY, "Cache Data Parity Error" }, \
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{ CXL_RAS_UC_CACHE_ADDR_PARITY, "Cache Address Parity Error" }, \
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{ CXL_RAS_UC_CACHE_BE_PARITY, "Cache Byte Enable Parity Error" }, \
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{ CXL_RAS_UC_CACHE_DATA_ECC, "Cache Data ECC Error" }, \
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{ CXL_RAS_UC_MEM_DATA_PARITY, "Memory Data Parity Error" }, \
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{ CXL_RAS_UC_MEM_ADDR_PARITY, "Memory Address Parity Error" }, \
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{ CXL_RAS_UC_MEM_BE_PARITY, "Memory Byte Enable Parity Error" }, \
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{ CXL_RAS_UC_MEM_DATA_ECC, "Memory Data ECC Error" }, \
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{ CXL_RAS_UC_REINIT_THRESH, "REINIT Threshold Hit" }, \
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{ CXL_RAS_UC_RSVD_ENCODE, "Received Unrecognized Encoding" }, \
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{ CXL_RAS_UC_POISON, "Received Poison From Peer" }, \
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{ CXL_RAS_UC_RECV_OVERFLOW, "Receiver Overflow" }, \
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{ CXL_RAS_UC_INTERNAL_ERR, "Component Specific Error" }, \
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{ CXL_RAS_UC_IDE_TX_ERR, "IDE Tx Error" }, \
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{ CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \
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)
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TRACE_EVENT(cxl_aer_uncorrectable_error,
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TP_PROTO(const struct device *dev, u32 status, u32 fe, u32 *hl),
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TP_ARGS(dev, status, fe, hl),
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TP_STRUCT__entry(
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__string(dev_name, dev_name(dev))
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__field(u32, status)
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__field(u32, first_error)
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__array(u32, header_log, CXL_HEADERLOG_SIZE_U32)
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),
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TP_fast_assign(
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__assign_str(dev_name, dev_name(dev));
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__entry->status = status;
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__entry->first_error = fe;
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/*
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* Embed the 512B headerlog data for user app retrieval and
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* parsing, but no need to print this in the trace buffer.
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*/
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memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);
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),
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TP_printk("%s: status: '%s' first_error: '%s'",
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__get_str(dev_name),
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show_uc_errs(__entry->status),
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show_uc_errs(__entry->first_error)
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)
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);
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#define CXL_RAS_CE_CACHE_DATA_ECC BIT(0)
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#define CXL_RAS_CE_MEM_DATA_ECC BIT(1)
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#define CXL_RAS_CE_CRC_THRESH BIT(2)
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#define CLX_RAS_CE_RETRY_THRESH BIT(3)
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#define CXL_RAS_CE_CACHE_POISON BIT(4)
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#define CXL_RAS_CE_MEM_POISON BIT(5)
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#define CXL_RAS_CE_PHYS_LAYER_ERR BIT(6)
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#define show_ce_errs(status) __print_flags(status, " | ", \
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{ CXL_RAS_CE_CACHE_DATA_ECC, "Cache Data ECC Error" }, \
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{ CXL_RAS_CE_MEM_DATA_ECC, "Memory Data ECC Error" }, \
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{ CXL_RAS_CE_CRC_THRESH, "CRC Threshold Hit" }, \
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{ CLX_RAS_CE_RETRY_THRESH, "Retry Threshold" }, \
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{ CXL_RAS_CE_CACHE_POISON, "Received Cache Poison From Peer" }, \
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{ CXL_RAS_CE_MEM_POISON, "Received Memory Poison From Peer" }, \
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{ CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \
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)
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TRACE_EVENT(cxl_aer_correctable_error,
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TP_PROTO(const struct device *dev, u32 status),
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TP_ARGS(dev, status),
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TP_STRUCT__entry(
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__string(dev_name, dev_name(dev))
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__field(u32, status)
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),
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TP_fast_assign(
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__assign_str(dev_name, dev_name(dev));
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__entry->status = status;
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),
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TP_printk("%s: status: '%s'",
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__get_str(dev_name), show_ce_errs(__entry->status)
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)
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);
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#endif /* _CXL_EVENTS_H */
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#define TRACE_INCLUDE_FILE trace
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#include <trace/define_trace.h>
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