Sudhakar Mamillapalli 0ad372b962 serial/8250_pci: Clear FIFOs for Intel ME Serial Over Lan device on BI
When using Serial Over Lan (SOL) over the virtual serial port in a Intel
management engine (ME) device, on device reset the serial FIFOs need to
be cleared to keep the FIFO indexes in-sync between the host and the
engine.

On a reset the serial device assertes BI, so using that as a cue FIFOs
are cleared.  So for this purpose a new handle_break callback has been
added.  One other problem is that the serial registers might temporarily
go to 0 on reset of this device.  So instead of using the IER register
read, if 0 returned use the ier value in uart_8250_port. This is hidden
under a custom serial_in.

Cc: Nhan H Mai <nhan.h.mai@intel.com>
Signed-off-by: Sudhakar Mamillapalli <sudhakar@fb.com>
Acked-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-04-18 16:26:17 -07:00
..
2012-01-24 12:55:36 -08:00
2012-03-28 18:30:01 +01:00
2012-04-18 15:57:31 -07:00
2012-04-09 11:14:49 -07:00
2012-03-28 18:30:03 +01:00
2012-01-26 11:29:47 -08:00
2012-03-28 18:30:03 +01:00
2011-03-31 11:26:23 -03:00
2012-02-10 10:25:27 -08:00
2011-03-31 11:26:23 -03:00
2011-09-22 16:08:57 -07:00
2011-08-26 11:01:15 -07:00
2012-01-09 14:44:15 -08:00
2012-04-18 15:57:31 -07:00
2012-04-18 15:57:31 -07:00
2012-01-26 17:14:50 -08:00
2012-03-27 16:47:35 -07:00
2011-09-22 16:08:57 -07:00
2012-03-23 17:19:37 -07:00
2012-03-28 18:30:03 +01:00
2012-03-28 18:30:03 +01:00
2012-03-28 18:30:03 +01:00
2012-01-26 17:14:50 -08:00
2012-01-26 17:14:50 -08:00
2012-03-28 18:30:03 +01:00