0aed55af88
The pmem driver has a need to transfer data with a persistent memory destination and be able to rely on the fact that the destination writes are not cached. It is sufficient for the writes to be flushed to a cpu-store-buffer (non-temporal / "movnt" in x86 terms), as we expect userspace to call fsync() to ensure data-writes have reached a power-fail-safe zone in the platform. The fsync() triggers a REQ_FUA or REQ_FLUSH to the pmem driver which will turn around and fence previous writes with an "sfence". Implement a __copy_from_user_inatomic_flushcache, memcpy_page_flushcache, and memcpy_flushcache, that guarantee that the destination buffer is not dirty in the cpu cache on completion. The new copy_from_iter_flushcache and sub-routines will be used to replace the "pmem api" (include/linux/pmem.h + arch/x86/include/asm/pmem.h). The availability of copy_from_iter_flushcache() and memcpy_flushcache() are gated by the CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE config symbol, and fallback to copy_from_iter_nocache() and plain memcpy() otherwise. This is meant to satisfy the concern from Linus that if a driver wants to do something beyond the normal nocache semantics it should be something private to that driver [1], and Al's concern that anything uaccess related belongs with the rest of the uaccess code [2]. The first consumer of this interface is a new 'copy_from_iter' dax operation so that pmem can inject cache maintenance operations without imposing this overhead on other dax-capable drivers. [1]: https://lists.01.org/pipermail/linux-nvdimm/2017-January/008364.html [2]: https://lists.01.org/pipermail/linux-nvdimm/2017-April/009942.html Cc: <x86@kernel.org> Cc: Jan Kara <jack@suse.cz> Cc: Jeff Moyer <jmoyer@redhat.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Christoph Hellwig <hch@lst.de> Cc: Toshi Kani <toshi.kani@hpe.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Al Viro <viro@zeniv.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Matthew Wilcox <mawilcox@microsoft.com> Reviewed-by: Ross Zwisler <ross.zwisler@linux.intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
204 lines
4.9 KiB
C
204 lines
4.9 KiB
C
/*
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* User address space access functions.
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*
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* Copyright 1997 Andi Kleen <ak@muc.de>
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* Copyright 1997 Linus Torvalds
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* Copyright 2002 Andi Kleen <ak@suse.de>
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*/
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#include <linux/export.h>
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#include <linux/uaccess.h>
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#include <linux/highmem.h>
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/*
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* Zero Userspace
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*/
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unsigned long __clear_user(void __user *addr, unsigned long size)
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{
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long __d0;
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might_fault();
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/* no memory constraint because it doesn't change any memory gcc knows
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about */
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stac();
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asm volatile(
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" testq %[size8],%[size8]\n"
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" jz 4f\n"
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"0: movq %[zero],(%[dst])\n"
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" addq %[eight],%[dst]\n"
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" decl %%ecx ; jnz 0b\n"
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"4: movq %[size1],%%rcx\n"
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" testl %%ecx,%%ecx\n"
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" jz 2f\n"
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"1: movb %b[zero],(%[dst])\n"
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" incq %[dst]\n"
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" decl %%ecx ; jnz 1b\n"
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"2:\n"
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".section .fixup,\"ax\"\n"
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"3: lea 0(%[size1],%[size8],8),%[size8]\n"
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" jmp 2b\n"
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".previous\n"
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_ASM_EXTABLE(0b,3b)
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_ASM_EXTABLE(1b,2b)
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: [size8] "=&c"(size), [dst] "=&D" (__d0)
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: [size1] "r"(size & 7), "[size8]" (size / 8), "[dst]"(addr),
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[zero] "r" (0UL), [eight] "r" (8UL));
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clac();
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return size;
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}
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EXPORT_SYMBOL(__clear_user);
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unsigned long clear_user(void __user *to, unsigned long n)
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{
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if (access_ok(VERIFY_WRITE, to, n))
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return __clear_user(to, n);
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return n;
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}
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EXPORT_SYMBOL(clear_user);
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/*
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* Try to copy last bytes and clear the rest if needed.
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* Since protection fault in copy_from/to_user is not a normal situation,
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* it is not necessary to optimize tail handling.
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*/
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__visible unsigned long
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copy_user_handle_tail(char *to, char *from, unsigned len)
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{
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for (; len; --len, to++) {
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char c;
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if (__get_user_nocheck(c, from++, sizeof(char)))
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break;
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if (__put_user_nocheck(c, to, sizeof(char)))
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break;
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}
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clac();
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return len;
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}
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#ifdef CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE
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/**
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* clean_cache_range - write back a cache range with CLWB
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* @vaddr: virtual start address
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* @size: number of bytes to write back
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*
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* Write back a cache range using the CLWB (cache line write back)
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* instruction. Note that @size is internally rounded up to be cache
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* line size aligned.
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*/
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static void clean_cache_range(void *addr, size_t size)
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{
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u16 x86_clflush_size = boot_cpu_data.x86_clflush_size;
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unsigned long clflush_mask = x86_clflush_size - 1;
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void *vend = addr + size;
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void *p;
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for (p = (void *)((unsigned long)addr & ~clflush_mask);
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p < vend; p += x86_clflush_size)
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clwb(p);
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}
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long __copy_user_flushcache(void *dst, const void __user *src, unsigned size)
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{
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unsigned long flushed, dest = (unsigned long) dst;
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long rc = __copy_user_nocache(dst, src, size, 0);
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/*
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* __copy_user_nocache() uses non-temporal stores for the bulk
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* of the transfer, but we need to manually flush if the
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* transfer is unaligned. A cached memory copy is used when
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* destination or size is not naturally aligned. That is:
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* - Require 8-byte alignment when size is 8 bytes or larger.
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* - Require 4-byte alignment when size is 4 bytes.
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*/
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if (size < 8) {
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if (!IS_ALIGNED(dest, 4) || size != 4)
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clean_cache_range(dst, 1);
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} else {
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if (!IS_ALIGNED(dest, 8)) {
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dest = ALIGN(dest, boot_cpu_data.x86_clflush_size);
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clean_cache_range(dst, 1);
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}
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flushed = dest - (unsigned long) dst;
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if (size > flushed && !IS_ALIGNED(size - flushed, 8))
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clean_cache_range(dst + size - 1, 1);
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}
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return rc;
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}
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void memcpy_flushcache(void *_dst, const void *_src, size_t size)
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{
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unsigned long dest = (unsigned long) _dst;
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unsigned long source = (unsigned long) _src;
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/* cache copy and flush to align dest */
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if (!IS_ALIGNED(dest, 8)) {
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unsigned len = min_t(unsigned, size, ALIGN(dest, 8) - dest);
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memcpy((void *) dest, (void *) source, len);
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clean_cache_range((void *) dest, len);
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dest += len;
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source += len;
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size -= len;
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if (!size)
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return;
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}
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/* 4x8 movnti loop */
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while (size >= 32) {
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asm("movq (%0), %%r8\n"
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"movq 8(%0), %%r9\n"
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"movq 16(%0), %%r10\n"
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"movq 24(%0), %%r11\n"
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"movnti %%r8, (%1)\n"
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"movnti %%r9, 8(%1)\n"
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"movnti %%r10, 16(%1)\n"
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"movnti %%r11, 24(%1)\n"
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:: "r" (source), "r" (dest)
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: "memory", "r8", "r9", "r10", "r11");
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dest += 32;
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source += 32;
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size -= 32;
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}
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/* 1x8 movnti loop */
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while (size >= 8) {
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asm("movq (%0), %%r8\n"
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"movnti %%r8, (%1)\n"
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:: "r" (source), "r" (dest)
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: "memory", "r8");
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dest += 8;
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source += 8;
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size -= 8;
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}
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/* 1x4 movnti loop */
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while (size >= 4) {
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asm("movl (%0), %%r8d\n"
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"movnti %%r8d, (%1)\n"
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:: "r" (source), "r" (dest)
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: "memory", "r8");
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dest += 4;
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source += 4;
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size -= 4;
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}
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/* cache copy for remaining bytes */
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if (size) {
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memcpy((void *) dest, (void *) source, size);
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clean_cache_range((void *) dest, size);
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}
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}
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EXPORT_SYMBOL_GPL(memcpy_flushcache);
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void memcpy_page_flushcache(char *to, struct page *page, size_t offset,
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size_t len)
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{
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char *from = kmap_atomic(page);
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memcpy_flushcache(to, from + offset, len);
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kunmap_atomic(from);
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}
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#endif
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