0b458d7b10
Instead of using hardcoded base addresses implicitly obtained through <linux/io.h>, pass the physical base for the three NPE blocks as memory resources and remap these in the driver. Drop the memory request region business, this will anyways be done by devm_* remapping functions. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
352 lines
8.3 KiB
C
352 lines
8.3 KiB
C
/*
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* arch/arm/mach-ixp4xx/common.c
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*
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* Generic code shared across all IXP4XX platforms
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*
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* Maintainer: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright 2002 (c) Intel Corporation
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* Copyright 2003-2004 (c) MontaVista, Software, Inc.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/tty.h>
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#include <linux/platform_device.h>
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#include <linux/serial_core.h>
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#include <linux/interrupt.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/export.h>
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#include <linux/cpu.h>
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#include <linux/pci.h>
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#include <linux/sched_clock.h>
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#include <linux/bitops.h>
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#include <linux/irqchip/irq-ixp4xx.h>
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#include <linux/platform_data/timer-ixp4xx.h>
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#include <mach/udc.h>
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#include <mach/hardware.h>
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#include <mach/io.h>
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#include <linux/uaccess.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/exception.h>
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#include <asm/irq.h>
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#include <asm/system_misc.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include "irqs.h"
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#define IXP4XX_TIMER_FREQ 66666000
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/*************************************************************************
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* IXP4xx chipset I/O mapping
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*************************************************************************/
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static struct map_desc ixp4xx_io_desc[] __initdata = {
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{ /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
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.virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
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.pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
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.length = IXP4XX_PERIPHERAL_REGION_SIZE,
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.type = MT_DEVICE
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}, { /* Expansion Bus Config Registers */
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.virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
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.pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
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.length = IXP4XX_EXP_CFG_REGION_SIZE,
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.type = MT_DEVICE
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}, { /* PCI Registers */
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.virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
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.pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
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.length = IXP4XX_PCI_CFG_REGION_SIZE,
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.type = MT_DEVICE
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}, { /* Queue Manager */
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.virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
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.pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
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.length = IXP4XX_QMGR_REGION_SIZE,
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.type = MT_DEVICE
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},
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};
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void __init ixp4xx_map_io(void)
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{
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iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
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}
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void __init ixp4xx_init_irq(void)
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{
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/*
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* ixp4xx does not implement the XScale PWRMODE register
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* so it must not call cpu_do_idle().
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*/
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cpu_idle_poll_ctrl(true);
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ixp4xx_irq_init(IXP4XX_INTC_BASE_PHYS,
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(cpu_is_ixp46x() || cpu_is_ixp43x()));
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}
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void __init ixp4xx_timer_init(void)
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{
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return ixp4xx_timer_setup(IXP4XX_TIMER_BASE_PHYS,
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IRQ_IXP4XX_TIMER1,
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IXP4XX_TIMER_FREQ);
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}
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static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
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void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
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{
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memcpy(&ixp4xx_udc_info, info, sizeof *info);
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}
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static struct resource ixp4xx_udc_resources[] = {
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[0] = {
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.start = 0xc800b000,
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.end = 0xc800bfff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_IXP4XX_USB,
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.end = IRQ_IXP4XX_USB,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource ixp4xx_gpio_resource[] = {
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{
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.start = IXP4XX_GPIO_BASE_PHYS,
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.end = IXP4XX_GPIO_BASE_PHYS + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device ixp4xx_gpio_device = {
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.name = "ixp4xx-gpio",
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.id = -1,
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.dev = {
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.resource = ixp4xx_gpio_resource,
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.num_resources = ARRAY_SIZE(ixp4xx_gpio_resource),
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};
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/*
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* USB device controller. The IXP4xx uses the same controller as PXA25X,
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* so we just use the same device.
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*/
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static struct platform_device ixp4xx_udc_device = {
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.name = "pxa25x-udc",
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.id = -1,
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.num_resources = 2,
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.resource = ixp4xx_udc_resources,
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.dev = {
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.platform_data = &ixp4xx_udc_info,
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},
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};
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static struct resource ixp4xx_npe_resources[] = {
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{
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.start = IXP4XX_NPEA_BASE_PHYS,
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.end = IXP4XX_NPEA_BASE_PHYS + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IXP4XX_NPEB_BASE_PHYS,
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.end = IXP4XX_NPEB_BASE_PHYS + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IXP4XX_NPEC_BASE_PHYS,
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.end = IXP4XX_NPEC_BASE_PHYS + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device ixp4xx_npe_device = {
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.name = "ixp4xx-npe",
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.id = -1,
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.num_resources = ARRAY_SIZE(ixp4xx_npe_resources),
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.resource = ixp4xx_npe_resources,
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};
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static struct platform_device ixp4xx_qmgr_device = {
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.name = "ixp4xx-qmgr",
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.id = -1,
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};
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static struct platform_device *ixp4xx_devices[] __initdata = {
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&ixp4xx_npe_device,
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&ixp4xx_qmgr_device,
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&ixp4xx_gpio_device,
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&ixp4xx_udc_device,
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};
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static struct resource ixp46x_i2c_resources[] = {
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[0] = {
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.start = 0xc8011000,
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.end = 0xc801101c,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_IXP4XX_I2C,
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.end = IRQ_IXP4XX_I2C,
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.flags = IORESOURCE_IRQ
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}
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};
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/*
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* I2C controller. The IXP46x uses the same block as the IOP3xx, so
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* we just use the same device name.
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*/
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static struct platform_device ixp46x_i2c_controller = {
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.name = "IOP3xx-I2C",
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.id = 0,
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.num_resources = 2,
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.resource = ixp46x_i2c_resources
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};
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static struct platform_device *ixp46x_devices[] __initdata = {
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&ixp46x_i2c_controller
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};
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unsigned long ixp4xx_exp_bus_size;
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EXPORT_SYMBOL(ixp4xx_exp_bus_size);
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void __init ixp4xx_sys_init(void)
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{
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ixp4xx_exp_bus_size = SZ_16M;
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platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
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if (cpu_is_ixp46x()) {
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int region;
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platform_add_devices(ixp46x_devices,
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ARRAY_SIZE(ixp46x_devices));
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for (region = 0; region < 7; region++) {
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if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
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ixp4xx_exp_bus_size = SZ_32M;
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break;
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}
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}
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}
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printk("IXP4xx: Using %luMiB expansion bus window size\n",
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ixp4xx_exp_bus_size >> 20);
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}
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unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
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EXPORT_SYMBOL(ixp4xx_timer_freq);
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void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
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{
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if (mode == REBOOT_SOFT) {
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/* Jump into ROM at address 0 */
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soft_restart(0);
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} else {
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/* Use on-chip reset capability */
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/* set the "key" register to enable access to
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* "timer" and "enable" registers
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*/
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*IXP4XX_OSWK = IXP4XX_WDT_KEY;
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/* write 0 to the timer register for an immediate reset */
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*IXP4XX_OSWT = 0;
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*IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
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}
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}
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#ifdef CONFIG_PCI
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static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
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{
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return (dma_addr + size) > SZ_64M;
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}
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static int ixp4xx_platform_notify_remove(struct device *dev)
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{
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if (dev_is_pci(dev))
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dmabounce_unregister_dev(dev);
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return 0;
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}
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#endif
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/*
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* Setup DMA mask to 64MB on PCI devices and 4 GB on all other things.
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*/
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static int ixp4xx_platform_notify(struct device *dev)
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{
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dev->dma_mask = &dev->coherent_dma_mask;
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#ifdef CONFIG_PCI
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if (dev_is_pci(dev)) {
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dev->coherent_dma_mask = DMA_BIT_MASK(28); /* 64 MB */
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dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce);
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return 0;
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}
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#endif
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dev->coherent_dma_mask = DMA_BIT_MASK(32);
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return 0;
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}
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int dma_set_coherent_mask(struct device *dev, u64 mask)
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{
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if (dev_is_pci(dev))
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mask &= DMA_BIT_MASK(28); /* 64 MB */
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if ((mask & DMA_BIT_MASK(28)) == DMA_BIT_MASK(28)) {
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dev->coherent_dma_mask = mask;
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return 0;
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}
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return -EIO; /* device wanted sub-64MB mask */
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}
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EXPORT_SYMBOL(dma_set_coherent_mask);
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#ifdef CONFIG_IXP4XX_INDIRECT_PCI
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/*
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* In the case of using indirect PCI, we simply return the actual PCI
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* address and our read/write implementation use that to drive the
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* access registers. If something outside of PCI is ioremap'd, we
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* fallback to the default.
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*/
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static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
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unsigned int mtype, void *caller)
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{
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if (!is_pci_memory(addr))
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return __arm_ioremap_caller(addr, size, mtype, caller);
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return (void __iomem *)addr;
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}
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static void ixp4xx_iounmap(volatile void __iomem *addr)
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{
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if (!is_pci_memory((__force u32)addr))
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__iounmap(addr);
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}
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#endif
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void __init ixp4xx_init_early(void)
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{
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platform_notify = ixp4xx_platform_notify;
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#ifdef CONFIG_PCI
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platform_notify_remove = ixp4xx_platform_notify_remove;
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#endif
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#ifdef CONFIG_IXP4XX_INDIRECT_PCI
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arch_ioremap_caller = ixp4xx_ioremap_caller;
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arch_iounmap = ixp4xx_iounmap;
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#endif
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}
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