0bbc9bc318
The SH7780 PCI host controller implements a configuration header that requires a fair bit of hand-holding to initialize properly. By default it appears as a pre-2.0 host controller given the zeroed out class code, so fix this up properly. Some boards that happened to be using the R7780RP version of the PCIC fixups had set this correctly, but this belongs in the standard initialization, and is by no means board specific. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
106 lines
3.0 KiB
C
106 lines
3.0 KiB
C
/*
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* Low-Level PCI Support for the SH7780
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*
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* Dustin McIntire (dustin@sensoria.com)
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* Derived from arch/i386/kernel/pci-*.c which bore the message:
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* (c) 1999--2000 Martin Mares <mj@ucw.cz>
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*
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* Ported to the new API by Paul Mundt <lethal@linux-sh.org>
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* With cleanup by Paul van Gool <pvangool@mimotech.com>
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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*/
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#undef DEBUG
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include "pci-sh4.h"
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/*
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* Initialization. Try all known PCI access methods. Note that we support
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* using both PCI BIOS and direct access: in such cases, we use I/O ports
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* to access config space.
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*
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* Note that the platform specific initialization (BSC registers, and memory
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* space mapping) will be called via the platform defined function
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* pcibios_init_platform().
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*/
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int __init sh7780_pci_init(struct pci_channel *chan)
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{
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unsigned int id;
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int ret, match = 0;
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pr_debug("PCI: Starting intialization.\n");
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chan->reg_base = 0xfe040000;
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chan->io_base = 0xfe200000;
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ctrl_outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
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/* check for SH7780/SH7780R hardware */
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id = pci_read_reg(chan, SH7780_PCIVID);
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if ((id & 0xffff) == SH7780_VENDOR_ID) {
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switch ((id >> 16) & 0xffff) {
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case SH7763_DEVICE_ID:
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case SH7780_DEVICE_ID:
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case SH7781_DEVICE_ID:
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case SH7785_DEVICE_ID:
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match = 1;
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break;
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}
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}
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if (unlikely(!match)) {
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printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
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return -ENODEV;
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}
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if ((ret = sh4_pci_check_direct(chan)) != 0)
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return ret;
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return pcibios_init_platform();
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}
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int __init sh7780_pcic_init(struct pci_channel *chan,
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struct sh4_pci_address_map *map)
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{
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u32 word;
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pci_write_reg(chan, PCI_CLASS_BRIDGE_HOST >> 8, SH7780_PCIBCC);
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pci_write_reg(chan, PCI_CLASS_BRIDGE_HOST & 0xff, SH7780_PCISUB);
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/* set the command/status bits to:
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* Wait Cycle Control + Parity Enable + Bus Master +
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* Mem space enable
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*/
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pci_write_reg(chan, 0x00000046, SH7780_PCICMD);
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/* Set IO and Mem windows to local address
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* Make PCI and local address the same for easy 1 to 1 mapping
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*/
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pci_write_reg(chan, map->window0.size - 0xfffff, SH4_PCILSR0);
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pci_write_reg(chan, map->window1.size - 0xfffff, SH4_PCILSR1);
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/* Set the values on window 0 PCI config registers */
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pci_write_reg(chan, map->window0.base, SH4_PCILAR0);
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pci_write_reg(chan, map->window0.base, SH7780_PCIMBAR0);
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/* Set the values on window 1 PCI config registers */
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pci_write_reg(chan, map->window1.base, SH4_PCILAR1);
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pci_write_reg(chan, map->window1.base, SH7780_PCIMBAR1);
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/* Apply any last-minute PCIC fixups */
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pci_fixup_pcic(chan);
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/* SH7780 init done, set central function init complete */
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/* use round robin mode to stop a device starving/overruning */
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word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
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pci_write_reg(chan, word, SH4_PCICR);
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return 0;
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}
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