d50a0923f3
MX64 & MX64W Hardware info: - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) - Storage: 1 GB (Micron MT29F8G08ABACA) - Networking: BCM58625 internal switch (5x 1GbE ports) - USB: 1x USB2.0 - Serial: Internal header - WLAN(MX64W only): 2x Broadcom BCM43520KMLG on the PCI bus This patch adds the Meraki MX64 series-specific bindings. Since some devices make use of the older A0 SoC, changes need to be made to accommodate this case, including removal of coherency options and modification to the secondary-boot-reg. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
25 lines
468 B
Plaintext
25 lines
468 B
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Device Tree Bindings for Cisco Meraki MX64 with B0+ SoC.
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*
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* Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
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*/
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/dts-v1/;
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#include "bcm958625-meraki-kingpin.dtsi"
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/ {
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model = "Cisco Meraki MX64";
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compatible = "meraki,mx64", "brcm,bcm58625", "brcm,nsp";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x80000000>;
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};
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};
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