Martin Blumenstingl 0d3051c790 clk: meson: meson8b: Fix the polarity of the RESET_N lines
CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST and
CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE are active low. This means:
- asserting them requires setting the register value to 0
- de-asserting them requires setting the register value to 1

Set the register value accordingly for these two reset lines by setting
the inverted the register value compared to all other reset lines.

Fixes: 189621726bc2f6 ("clk: meson: meson8b: register the built-in reset controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200417184127.1319871-3-martin.blumenstingl@googlemail.com
2020-04-29 10:26:53 +02:00
..
2020-01-04 23:34:39 -08:00
2020-01-04 23:34:39 -08:00
2020-03-06 12:06:01 -08:00
2019-05-30 16:33:37 -07:00
2020-04-03 15:22:05 -07:00
2018-12-11 09:57:47 -08:00
2020-01-28 13:26:48 -08:00
2019-07-15 20:18:40 -07:00