Stephen Boyd
0d7a660bfe
Merge branches 'clk-doc', 'clk-renesas', 'clk-allwinner', 'clk-rockchip' and 'clk-xilinx' into clk-next
...
- Convert Xilinx VCU clk driver to a proper clk provider driver
- Expose Xilinx ZynqMP clk driver to more platforms
* clk-doc:
linux/clk.h: use correct kernel-doc notation for 2 functions
* clk-renesas: (21 commits)
clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentation
clk: renesas: r8a779a0: Add RAVB clocks
clk: renesas: r8a779a0: Add I2C clocks
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add support for RZ/G2 M/N/H
clk: renesas: r8a779a0: Add SYS-DMAC clocks
clk: renesas: r8a779a0: Add SDHI support
clk: renesas: rcar-gen3: Factor out CPG library
clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clock
clk: renesas: r8a779a0: Add MSIOF clocks
clk: renesas: r8a779a0: Add PFC/GPIO clocks
clk: renesas: r8a779a0: Fix parent of CBFUSA clock
clk: renesas: r8a779a0: Remove non-existent S2 clock
clk: renesas: r8a779a0: Add HSCIF support
clk: renesas: r8a779a0: Add RWDT clocks
clk: renesas: r8a779a0: Add VSPX clock support
clk: renesas: r8a779a0: Add VSPD clock support
clk: renesas: r8a779a0: Add FCPVD clock support
clk: renesas: r8a77995: Add TMU clocks
clk: renesas: r8a77990: Add TMU clocks
clk: renesas: r8a77965: Add TMU clocks
...
* clk-allwinner:
clk: sunxi-ng: Add support for the Allwinner H616 CCU
clk: sunxi-ng: Add support for the Allwinner H616 R-CCU
dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616
clk: sunxi-ng: h6: Fix clock divider range on some clocks
clk: sunxi: clk-mod0: Demote non-conformant kernel-doc header
clk: sunxi: clk-a10-ve: Demote obvious kernel-doc abuse
clk: sunxi: clk-sunxi: Demote a bunch of non-conformant kernel-doc headers
clk: sunxi-ng: h6: Fix CEC clock
clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and reset
* clk-rockchip:
clk: rockchip: fix DPHY gate locations on rk3368
clk: rockchip: use clock id for SCLK_VIP_OUT on rk3368
clk: rockchip: add clock id for SCLK_VIP_OUT on rk3368
clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
clk: rockchip: add clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
clk: rockchip: Demote non-conformant kernel-doc header in half-divider
clk: rockchip: Demote kernel-doc abuses to standard comment blocks in plls
clk: rockchip: Remove unused/undocumented struct members from clk-cpu
clk: rockchip: Demote non-conformant kernel-doc headers in main clock code
* clk-xilinx:
clk: xilinx: move xlnx_vcu clock driver from soc
soc: xilinx: vcu: fix alignment to open parenthesis
soc: xilinx: vcu: fix repeated word the in comment
soc: xilinx: vcu: use bitfields for register definition
soc: xilinx: vcu: remove calculation of PLL configuration
soc: xilinx: vcu: make the PLL configurable
soc: xilinx: vcu: make pll post divider explicit
soc: xilinx: vcu: implement clock provider for output clocks
soc: xilinx: vcu: register PLL as fixed rate clock
soc: xilinx: vcu: implement PLL disable
soc: xilinx: vcu: add helpers for configuring PLL
soc: xilinx: vcu: add helper to wait for PLL locked
soc: xilinx: vcu: drop coreclk from struct xlnx_vcu
clk: divider: fix initialization with parent_hw
ARM: dts: vcu: define indexes for output clocks
clk: axi-clkgen: use devm_platform_ioremap_resource() short-hand
dt-bindings: clock: adi,axi-clkgen: add compatible string for ZynqMP support
clk: clk-axiclkgen: add ZynqMP PFD and VCO limits
clk: axi-clkgen: replace ARCH dependencies with driver deps
2021-02-16 14:06:43 -08:00
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