0b12620fdd
ESR_EL2 was defined as a 32-bit register in the initial release of the ARM Architecture Manual for Armv8-A, and was later extended to 64 bits, with bits [63:32] RES0. ARMv8.7 introduced FEAT_LS64, which makes use of bits [36:32]. KVM treats ESR_EL1 as a 64-bit register when saving and restoring the guest context, but ESR_EL2 is handled as a 32-bit register. Start treating ESR_EL2 as a 64-bit register to allow KVM to make use of the most significant 32 bits in the future. The type chosen to represent ESR_EL2 is u64, as that is consistent with the notation KVM overwhelmingly uses today (u32), and how the rest of the registers are declared. Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220425114444.368693-5-alexandru.elisei@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
26 lines
594 B
C
26 lines
594 B
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/* Copyright (C) 2018 - Arm Ltd */
|
|
|
|
#ifndef __ARM64_KVM_RAS_H__
|
|
#define __ARM64_KVM_RAS_H__
|
|
|
|
#include <linux/acpi.h>
|
|
#include <linux/errno.h>
|
|
#include <linux/types.h>
|
|
|
|
#include <asm/acpi.h>
|
|
|
|
/*
|
|
* Was this synchronous external abort a RAS notification?
|
|
* Returns '0' for errors handled by some RAS subsystem, or -ENOENT.
|
|
*/
|
|
static inline int kvm_handle_guest_sea(phys_addr_t addr, u64 esr)
|
|
{
|
|
/* apei_claim_sea(NULL) expects to mask interrupts itself */
|
|
lockdep_assert_irqs_enabled();
|
|
|
|
return apei_claim_sea(NULL);
|
|
}
|
|
|
|
#endif /* __ARM64_KVM_RAS_H__ */
|