Markos Chandras ed4cbc81ad MIPS: HTW: Prevent accidental HTW start due to nested htw_{start, stop}
activate_mm() and switch_mm() call get_new_mmu_context() which in turn
can enable the HTW before the entryhi is changed with the new ASID.
Since the latter will enable the HTW in local_flush_tlb_all(),
then there is a small timing window where the HTW is running with the
new ASID but with an old pgd since the TLBMISS_HANDLER_SETUP_PGD
hasn't assigned a new one yet. In order to prevent that, we introduce a
simple htw counter to avoid starting HTW accidentally due to nested
htw_{start,stop}() sequences. Moreover, since various IPI calls can
enforce TLB flushing operations on a different core, such an operation
may interrupt another htw_{stop,start} in progress leading inconsistent
updates of the htw_seq variable. In order to avoid that, we disable the
interrupts whenever we update that variable.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # 3.17+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9118/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-02-16 10:55:26 +01:00
..
2013-02-01 10:00:22 +01:00
2013-02-01 10:00:22 +01:00
2013-02-01 10:00:22 +01:00
2013-02-01 10:00:22 +01:00
2013-02-01 10:00:22 +01:00
2014-05-24 00:07:01 +02:00
2014-11-07 15:07:36 +01:00
2014-05-24 00:07:01 +02:00
2011-12-07 22:03:45 +00:00
2014-11-24 07:44:52 +01:00
2013-02-01 10:00:22 +01:00
2013-02-01 10:00:22 +01:00
2013-02-01 10:00:22 +01:00
2014-08-26 13:45:51 -04:00
2014-11-24 07:45:00 +01:00
2014-05-24 00:07:01 +02:00
2014-05-24 00:07:01 +02:00
2013-02-01 10:00:22 +01:00
2014-05-02 16:39:10 +01:00
2014-08-02 00:06:37 +02:00
2014-10-27 03:37:42 +01:00
2014-10-27 03:37:42 +01:00
2014-10-27 03:37:42 +01:00
2014-10-27 03:37:42 +01:00
2014-08-06 13:04:30 +02:00
2014-08-06 13:04:30 +02:00
2014-05-24 00:07:01 +02:00
2014-05-24 00:07:01 +02:00
2014-11-24 07:45:38 +01:00
2014-05-24 00:07:01 +02:00