0eb0d9f4de
This platform driver adds the initial support of Secure Digital Host Controller Interface compliant controller found in Qualcomm chipsets. Signed-off-by: Asutosh Das <asutoshd@codeaurora.org> Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org> Tested-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Chris Ball <chris@printf.net>
209 lines
5.7 KiB
C
209 lines
5.7 KiB
C
/*
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* drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
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*
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* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/delay.h>
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#include "sdhci-pltfm.h"
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#define CORE_HC_MODE 0x78
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#define HC_MODE_EN 0x1
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#define CORE_POWER 0x0
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#define CORE_SW_RST BIT(7)
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struct sdhci_msm_host {
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struct platform_device *pdev;
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void __iomem *core_mem; /* MSM SDCC mapped address */
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struct clk *clk; /* main SD/MMC bus clock */
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struct clk *pclk; /* SDHC peripheral bus clock */
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struct clk *bus_clk; /* SDHC bus voter clock */
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struct mmc_host *mmc;
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struct sdhci_pltfm_data sdhci_msm_pdata;
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};
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/* Platform specific tuning */
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static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
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{
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/*
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* Tuning is required for SDR104, HS200 and HS400 cards and if the clock
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* frequency greater than 100MHz in those modes. The standard tuning
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* procedure should not be executed, but a custom implementation will be
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* added here instead.
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*/
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return 0;
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}
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static const struct of_device_id sdhci_msm_dt_match[] = {
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{ .compatible = "qcom,sdhci-msm-v4" },
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{},
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};
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MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
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static struct sdhci_ops sdhci_msm_ops = {
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.platform_execute_tuning = sdhci_msm_execute_tuning,
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};
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static int sdhci_msm_probe(struct platform_device *pdev)
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{
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struct sdhci_host *host;
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_msm_host *msm_host;
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struct resource *core_memres;
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int ret;
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u16 host_version;
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msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
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if (!msm_host)
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return -ENOMEM;
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msm_host->sdhci_msm_pdata.ops = &sdhci_msm_ops;
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host = sdhci_pltfm_init(pdev, &msm_host->sdhci_msm_pdata, 0);
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if (IS_ERR(host))
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return PTR_ERR(host);
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pltfm_host = sdhci_priv(host);
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pltfm_host->priv = msm_host;
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msm_host->mmc = host->mmc;
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msm_host->pdev = pdev;
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ret = mmc_of_parse(host->mmc);
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if (ret)
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goto pltfm_free;
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sdhci_get_of_property(pdev);
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/* Setup SDCC bus voter clock. */
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msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
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if (!IS_ERR(msm_host->bus_clk)) {
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/* Vote for max. clk rate for max. performance */
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ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
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if (ret)
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goto pltfm_free;
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ret = clk_prepare_enable(msm_host->bus_clk);
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if (ret)
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goto pltfm_free;
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}
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/* Setup main peripheral bus clock */
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msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
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if (IS_ERR(msm_host->pclk)) {
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ret = PTR_ERR(msm_host->pclk);
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dev_err(&pdev->dev, "Perpheral clk setup failed (%d)\n", ret);
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goto bus_clk_disable;
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}
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ret = clk_prepare_enable(msm_host->pclk);
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if (ret)
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goto bus_clk_disable;
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/* Setup SDC MMC clock */
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msm_host->clk = devm_clk_get(&pdev->dev, "core");
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if (IS_ERR(msm_host->clk)) {
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ret = PTR_ERR(msm_host->clk);
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dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
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goto pclk_disable;
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}
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ret = clk_prepare_enable(msm_host->clk);
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if (ret)
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goto pclk_disable;
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core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
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if (IS_ERR(msm_host->core_mem)) {
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dev_err(&pdev->dev, "Failed to remap registers\n");
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ret = PTR_ERR(msm_host->core_mem);
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goto clk_disable;
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}
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/* Reset the core and Enable SDHC mode */
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writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) |
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CORE_SW_RST, msm_host->core_mem + CORE_POWER);
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/* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
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usleep_range(1000, 5000);
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if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) {
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dev_err(&pdev->dev, "Stuck in reset\n");
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ret = -ETIMEDOUT;
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goto clk_disable;
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}
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/* Set HC_MODE_EN bit in HC_MODE register */
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writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
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host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
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host->quirks |= SDHCI_QUIRK_SINGLE_POWER_WRITE;
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host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
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dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
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host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
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SDHCI_VENDOR_VER_SHIFT));
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ret = sdhci_add_host(host);
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if (ret)
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goto clk_disable;
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return 0;
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clk_disable:
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clk_disable_unprepare(msm_host->clk);
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pclk_disable:
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clk_disable_unprepare(msm_host->pclk);
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bus_clk_disable:
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if (!IS_ERR(msm_host->bus_clk))
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clk_disable_unprepare(msm_host->bus_clk);
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pltfm_free:
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sdhci_pltfm_free(pdev);
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return ret;
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}
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static int sdhci_msm_remove(struct platform_device *pdev)
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{
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struct sdhci_host *host = platform_get_drvdata(pdev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = pltfm_host->priv;
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int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
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0xffffffff);
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sdhci_remove_host(host, dead);
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sdhci_pltfm_free(pdev);
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clk_disable_unprepare(msm_host->clk);
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clk_disable_unprepare(msm_host->pclk);
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if (!IS_ERR(msm_host->bus_clk))
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clk_disable_unprepare(msm_host->bus_clk);
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return 0;
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}
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static struct platform_driver sdhci_msm_driver = {
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.probe = sdhci_msm_probe,
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.remove = sdhci_msm_remove,
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.driver = {
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.name = "sdhci_msm",
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.owner = THIS_MODULE,
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.of_match_table = sdhci_msm_dt_match,
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},
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};
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module_platform_driver(sdhci_msm_driver);
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MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
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MODULE_LICENSE("GPL v2");
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