30ad29bb48
Currently, code of Loongson-2/3 is under loongson directory and code of Loongson-1 is under loongson1 directory. Besides, there are Kconfig options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is very ugly and confusing. Since Loongson-2/3 are both 64-bit general- purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names and Kconfig symbols from loongson/loongson1 to loongson64/loongson32. [ralf@linux-mips.org: Resolve a number of simple conflicts.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/9790/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
30 lines
837 B
C
30 lines
837 B
C
/*
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* Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>
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*
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* Loongson 1 PWM Register Definitions.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __ASM_MACH_LOONGSON32_REGS_PWM_H
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#define __ASM_MACH_LOONGSON32_REGS_PWM_H
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/* Loongson 1 PWM Timer Register Definitions */
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#define PWM_CNT 0x0
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#define PWM_HRC 0x4
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#define PWM_LRC 0x8
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#define PWM_CTRL 0xc
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/* PWM Control Register Bits */
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#define CNT_RST (0x1 << 7)
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#define INT_SR (0x1 << 6)
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#define INT_EN (0x1 << 5)
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#define PWM_SINGLE (0x1 << 4)
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#define PWM_OE (0x1 << 3)
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#define CNT_EN 0x1
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#endif /* __ASM_MACH_LOONGSON32_REGS_PWM_H */
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