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linux/arch/mips/ralink
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Sashka Nochkin 86ce9a340e mips: mt7620: fallback to SDRAM when syscfg0 does not have a valid value for the memory type 
Mediatek MT7620 SoC has syscfg0 bits where it sets the type of memory being used.
However, sometimes those bits are not set properly (reading "11"). In this case, the SoC assumes SDRAM.
The patch below reflects that.

Signed-off-by: Sashka Nochkin <linux-mips@durdom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13135/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-13 15:39:43 +02:00
..
bootrom.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
cevt-rt3352.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
clk.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
common.h MIPS: Change my email address 2016-05-13 14:02:18 +02:00
early_printk.c MIPS: ralink: Add tty detection 2015-11-11 08:38:03 +01:00
ill_acc.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
irq-gic.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
irq.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
Kconfig MIPS: pci: Add MT7620a PCIE driver 2016-01-20 00:39:20 +01:00
Makefile MIPS: Change my email address 2016-05-13 14:02:18 +02:00
mt7620.c mips: mt7620: fallback to SDRAM when syscfg0 does not have a valid value for the memory type 2016-05-13 15:39:43 +02:00
mt7621.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
of.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
Platform MIPS: ralink: add MT7621 support 2016-01-20 00:39:20 +01:00
prom.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
reset.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
rt288x.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
rt305x.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
rt3883.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
timer-gic.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00
timer.c MIPS: Change my email address 2016-05-13 14:02:18 +02:00