Rahul Tanwar 106ef3bda2 clk: mxl: Fix a clk entry by adding relevant flags ... One of the clock entry "dcl" clk has some HW limitations. One is that its rate can only by changed by changing its parent clk's rate & two is that HW does not support enable/disable for this clk. Handle above two limitations by adding relevant flags. Add standard flag CLK_SET_RATE_PARENT to handle rate change and add driver internal flag DIV_CLK_NO_MASK to handle enable/disable. Fixes: d058fd9e89 ("clk: intel: Add CGU clock driver for a new SoC") Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com> Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com> Link: https://lore.kernel.org/r/a4770e7225f8a0c03c8ab2ba80434a4e8e9afb17.1665642720.git.rtanwar@maxlinear.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>		2022-10-17 15:27:48 -07:00
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clk-cgu-pll.c	clk: mxl: Remove redundant spinlocks	2022-10-17 14:17:37 -07:00
clk-cgu.c	clk: mxl: Fix a clk entry by adding relevant flags	2022-10-17 15:27:48 -07:00
clk-cgu.h	clk: mxl: Fix a clk entry by adding relevant flags	2022-10-17 15:27:48 -07:00
clk-fch.c	clk: x86: Fix clk_gate_flags for RV_CLK_GATE	2022-01-06 17:57:53 -08:00
clk-lgm.c	clk: mxl: Fix a clk entry by adding relevant flags	2022-10-17 15:27:48 -07:00
clk-lpss-atom.c	clk: x86: Rename clk-lpt to more specific clk-lpss-atom	2021-07-27 14:03:47 -07:00
clk-pmc-atom.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	2019-06-05 17:36:37 +02:00
Kconfig	clk: mxl: Switch from direct readl/writel based IO to regmap based IO	2022-10-17 14:17:37 -07:00
Makefile	platform/x86: Drop the PMC_ATOM Kconfig option	2022-06-12 14:41:22 +02:00