87d5972e47
Add pci_epc_ops to map physical address to MSI address and return MSI data. The physical address is an address in the outbound region. This is required to implement doorbell functionality of NTB (non-transparent bridge) wherein EPC on either side of the interface (primary and secondary) can directly write to the physical address (in outbound region) of the other interface to ring doorbell using MSI. Link: https://lore.kernel.org/r/20210201195809.7342-9-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
802 lines
21 KiB
C
802 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCI Endpoint *Controller* (EPC) library
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*
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* Copyright (C) 2017 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*/
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#include <linux/device.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pci-epc.h>
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#include <linux/pci-epf.h>
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#include <linux/pci-ep-cfs.h>
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static struct class *pci_epc_class;
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static void devm_pci_epc_release(struct device *dev, void *res)
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{
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struct pci_epc *epc = *(struct pci_epc **)res;
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pci_epc_destroy(epc);
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}
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static int devm_pci_epc_match(struct device *dev, void *res, void *match_data)
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{
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struct pci_epc **epc = res;
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return *epc == match_data;
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}
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/**
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* pci_epc_put() - release the PCI endpoint controller
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* @epc: epc returned by pci_epc_get()
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*
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* release the refcount the caller obtained by invoking pci_epc_get()
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*/
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void pci_epc_put(struct pci_epc *epc)
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{
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if (!epc || IS_ERR(epc))
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return;
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module_put(epc->ops->owner);
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put_device(&epc->dev);
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}
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EXPORT_SYMBOL_GPL(pci_epc_put);
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/**
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* pci_epc_get() - get the PCI endpoint controller
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* @epc_name: device name of the endpoint controller
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*
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* Invoke to get struct pci_epc * corresponding to the device name of the
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* endpoint controller
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*/
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struct pci_epc *pci_epc_get(const char *epc_name)
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{
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int ret = -EINVAL;
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struct pci_epc *epc;
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struct device *dev;
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struct class_dev_iter iter;
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class_dev_iter_init(&iter, pci_epc_class, NULL, NULL);
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while ((dev = class_dev_iter_next(&iter))) {
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if (strcmp(epc_name, dev_name(dev)))
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continue;
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epc = to_pci_epc(dev);
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if (!try_module_get(epc->ops->owner)) {
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ret = -EINVAL;
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goto err;
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}
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class_dev_iter_exit(&iter);
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get_device(&epc->dev);
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return epc;
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}
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err:
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class_dev_iter_exit(&iter);
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return ERR_PTR(ret);
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}
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EXPORT_SYMBOL_GPL(pci_epc_get);
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/**
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* pci_epc_get_first_free_bar() - helper to get first unreserved BAR
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* @epc_features: pci_epc_features structure that holds the reserved bar bitmap
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*
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* Invoke to get the first unreserved BAR that can be used by the endpoint
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* function. For any incorrect value in reserved_bar return '0'.
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*/
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enum pci_barno
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pci_epc_get_first_free_bar(const struct pci_epc_features *epc_features)
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{
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return pci_epc_get_next_free_bar(epc_features, BAR_0);
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}
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EXPORT_SYMBOL_GPL(pci_epc_get_first_free_bar);
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/**
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* pci_epc_get_next_free_bar() - helper to get unreserved BAR starting from @bar
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* @epc_features: pci_epc_features structure that holds the reserved bar bitmap
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* @bar: the starting BAR number from where unreserved BAR should be searched
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*
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* Invoke to get the next unreserved BAR starting from @bar that can be used
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* for endpoint function. For any incorrect value in reserved_bar return '0'.
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*/
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enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
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*epc_features, enum pci_barno bar)
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{
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unsigned long free_bar;
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if (!epc_features)
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return BAR_0;
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/* If 'bar - 1' is a 64-bit BAR, move to the next BAR */
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if ((epc_features->bar_fixed_64bit << 1) & 1 << bar)
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bar++;
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/* Find if the reserved BAR is also a 64-bit BAR */
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free_bar = epc_features->reserved_bar & epc_features->bar_fixed_64bit;
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/* Set the adjacent bit if the reserved BAR is also a 64-bit BAR */
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free_bar <<= 1;
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free_bar |= epc_features->reserved_bar;
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free_bar = find_next_zero_bit(&free_bar, 6, bar);
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if (free_bar > 5)
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return NO_BAR;
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return free_bar;
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}
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EXPORT_SYMBOL_GPL(pci_epc_get_next_free_bar);
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/**
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* pci_epc_get_features() - get the features supported by EPC
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* @epc: the features supported by *this* EPC device will be returned
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* @func_no: the features supported by the EPC device specific to the
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* endpoint function with func_no will be returned
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*
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* Invoke to get the features provided by the EPC which may be
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* specific to an endpoint function. Returns pci_epc_features on success
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* and NULL for any failures.
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*/
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const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
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u8 func_no)
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{
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const struct pci_epc_features *epc_features;
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if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
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return NULL;
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if (!epc->ops->get_features)
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return NULL;
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mutex_lock(&epc->lock);
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epc_features = epc->ops->get_features(epc, func_no);
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mutex_unlock(&epc->lock);
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return epc_features;
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}
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EXPORT_SYMBOL_GPL(pci_epc_get_features);
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/**
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* pci_epc_stop() - stop the PCI link
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* @epc: the link of the EPC device that has to be stopped
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*
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* Invoke to stop the PCI link
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*/
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void pci_epc_stop(struct pci_epc *epc)
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{
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if (IS_ERR(epc) || !epc->ops->stop)
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return;
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mutex_lock(&epc->lock);
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epc->ops->stop(epc);
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mutex_unlock(&epc->lock);
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}
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EXPORT_SYMBOL_GPL(pci_epc_stop);
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/**
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* pci_epc_start() - start the PCI link
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* @epc: the link of *this* EPC device has to be started
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*
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* Invoke to start the PCI link
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*/
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int pci_epc_start(struct pci_epc *epc)
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{
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int ret;
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if (IS_ERR(epc))
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return -EINVAL;
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if (!epc->ops->start)
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return 0;
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mutex_lock(&epc->lock);
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ret = epc->ops->start(epc);
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mutex_unlock(&epc->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(pci_epc_start);
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/**
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* pci_epc_raise_irq() - interrupt the host system
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* @epc: the EPC device which has to interrupt the host
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* @func_no: the endpoint function number in the EPC device
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* @type: specify the type of interrupt; legacy, MSI or MSI-X
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* @interrupt_num: the MSI or MSI-X interrupt number
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*
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* Invoke to raise an legacy, MSI or MSI-X interrupt
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*/
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int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
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enum pci_epc_irq_type type, u16 interrupt_num)
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{
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int ret;
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if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
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return -EINVAL;
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if (!epc->ops->raise_irq)
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return 0;
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mutex_lock(&epc->lock);
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ret = epc->ops->raise_irq(epc, func_no, type, interrupt_num);
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mutex_unlock(&epc->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(pci_epc_raise_irq);
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/**
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* pci_epc_map_msi_irq() - Map physical address to MSI address and return
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* MSI data
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* @epc: the EPC device which has the MSI capability
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* @func_no: the physical endpoint function number in the EPC device
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* @phys_addr: the physical address of the outbound region
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* @interrupt_num: the MSI interrupt number
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* @entry_size: Size of Outbound address region for each interrupt
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* @msi_data: the data that should be written in order to raise MSI interrupt
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* with interrupt number as 'interrupt num'
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* @msi_addr_offset: Offset of MSI address from the aligned outbound address
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* to which the MSI address is mapped
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*
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* Invoke to map physical address to MSI address and return MSI data. The
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* physical address should be an address in the outbound region. This is
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* required to implement doorbell functionality of NTB wherein EPC on either
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* side of the interface (primary and secondary) can directly write to the
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* physical address (in outbound region) of the other interface to ring
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* doorbell.
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*/
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int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, phys_addr_t phys_addr,
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u8 interrupt_num, u32 entry_size, u32 *msi_data,
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u32 *msi_addr_offset)
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{
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int ret;
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if (IS_ERR_OR_NULL(epc))
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return -EINVAL;
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if (!epc->ops->map_msi_irq)
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return -EINVAL;
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mutex_lock(&epc->lock);
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ret = epc->ops->map_msi_irq(epc, func_no, phys_addr, interrupt_num,
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entry_size, msi_data, msi_addr_offset);
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mutex_unlock(&epc->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(pci_epc_map_msi_irq);
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/**
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* pci_epc_get_msi() - get the number of MSI interrupt numbers allocated
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* @epc: the EPC device to which MSI interrupts was requested
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* @func_no: the endpoint function number in the EPC device
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*
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* Invoke to get the number of MSI interrupts allocated by the RC
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*/
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int pci_epc_get_msi(struct pci_epc *epc, u8 func_no)
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{
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int interrupt;
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if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
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return 0;
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if (!epc->ops->get_msi)
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return 0;
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mutex_lock(&epc->lock);
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interrupt = epc->ops->get_msi(epc, func_no);
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mutex_unlock(&epc->lock);
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if (interrupt < 0)
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return 0;
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interrupt = 1 << interrupt;
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return interrupt;
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}
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EXPORT_SYMBOL_GPL(pci_epc_get_msi);
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/**
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* pci_epc_set_msi() - set the number of MSI interrupt numbers required
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* @epc: the EPC device on which MSI has to be configured
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* @func_no: the endpoint function number in the EPC device
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* @interrupts: number of MSI interrupts required by the EPF
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*
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* Invoke to set the required number of MSI interrupts.
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*/
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int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
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{
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int ret;
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u8 encode_int;
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if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
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interrupts > 32)
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return -EINVAL;
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if (!epc->ops->set_msi)
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return 0;
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encode_int = order_base_2(interrupts);
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mutex_lock(&epc->lock);
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ret = epc->ops->set_msi(epc, func_no, encode_int);
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mutex_unlock(&epc->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(pci_epc_set_msi);
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/**
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* pci_epc_get_msix() - get the number of MSI-X interrupt numbers allocated
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* @epc: the EPC device to which MSI-X interrupts was requested
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* @func_no: the endpoint function number in the EPC device
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*
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* Invoke to get the number of MSI-X interrupts allocated by the RC
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*/
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int pci_epc_get_msix(struct pci_epc *epc, u8 func_no)
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{
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int interrupt;
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if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
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return 0;
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if (!epc->ops->get_msix)
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return 0;
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mutex_lock(&epc->lock);
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interrupt = epc->ops->get_msix(epc, func_no);
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mutex_unlock(&epc->lock);
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if (interrupt < 0)
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return 0;
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return interrupt + 1;
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}
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EXPORT_SYMBOL_GPL(pci_epc_get_msix);
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/**
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* pci_epc_set_msix() - set the number of MSI-X interrupt numbers required
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* @epc: the EPC device on which MSI-X has to be configured
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* @func_no: the endpoint function number in the EPC device
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* @interrupts: number of MSI-X interrupts required by the EPF
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* @bir: BAR where the MSI-X table resides
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* @offset: Offset pointing to the start of MSI-X table
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*
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* Invoke to set the required number of MSI-X interrupts.
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*/
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int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts,
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enum pci_barno bir, u32 offset)
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{
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int ret;
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if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
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interrupts < 1 || interrupts > 2048)
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return -EINVAL;
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if (!epc->ops->set_msix)
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return 0;
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mutex_lock(&epc->lock);
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ret = epc->ops->set_msix(epc, func_no, interrupts - 1, bir, offset);
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mutex_unlock(&epc->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(pci_epc_set_msix);
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/**
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* pci_epc_unmap_addr() - unmap CPU address from PCI address
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* @epc: the EPC device on which address is allocated
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* @func_no: the endpoint function number in the EPC device
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* @phys_addr: physical address of the local system
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*
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* Invoke to unmap the CPU address from PCI address.
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*/
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void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
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phys_addr_t phys_addr)
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{
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if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
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return;
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if (!epc->ops->unmap_addr)
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return;
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mutex_lock(&epc->lock);
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epc->ops->unmap_addr(epc, func_no, phys_addr);
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mutex_unlock(&epc->lock);
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}
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EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
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/**
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* pci_epc_map_addr() - map CPU address to PCI address
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* @epc: the EPC device on which address is allocated
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* @func_no: the endpoint function number in the EPC device
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* @phys_addr: physical address of the local system
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* @pci_addr: PCI address to which the physical address should be mapped
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* @size: the size of the allocation
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*
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* Invoke to map CPU address with PCI address.
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*/
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int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
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phys_addr_t phys_addr, u64 pci_addr, size_t size)
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{
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int ret;
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if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
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return -EINVAL;
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if (!epc->ops->map_addr)
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return 0;
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mutex_lock(&epc->lock);
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ret = epc->ops->map_addr(epc, func_no, phys_addr, pci_addr, size);
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mutex_unlock(&epc->lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(pci_epc_map_addr);
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/**
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* pci_epc_clear_bar() - reset the BAR
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* @epc: the EPC device for which the BAR has to be cleared
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* @func_no: the endpoint function number in the EPC device
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* @epf_bar: the struct epf_bar that contains the BAR information
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*
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* Invoke to reset the BAR of the endpoint device.
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*/
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void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
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struct pci_epf_bar *epf_bar)
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{
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if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
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(epf_bar->barno == BAR_5 &&
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epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
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return;
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if (!epc->ops->clear_bar)
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return;
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mutex_lock(&epc->lock);
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epc->ops->clear_bar(epc, func_no, epf_bar);
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mutex_unlock(&epc->lock);
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}
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EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
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/**
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* pci_epc_set_bar() - configure BAR in order for host to assign PCI addr space
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* @epc: the EPC device on which BAR has to be configured
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* @func_no: the endpoint function number in the EPC device
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* @epf_bar: the struct epf_bar that contains the BAR information
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*
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* Invoke to configure the BAR of the endpoint device.
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*/
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int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
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struct pci_epf_bar *epf_bar)
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{
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int ret;
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int flags = epf_bar->flags;
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if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
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(epf_bar->barno == BAR_5 &&
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flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ||
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(flags & PCI_BASE_ADDRESS_SPACE_IO &&
|
|
flags & PCI_BASE_ADDRESS_IO_MASK) ||
|
|
(upper_32_bits(epf_bar->size) &&
|
|
!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))
|
|
return -EINVAL;
|
|
|
|
if (!epc->ops->set_bar)
|
|
return 0;
|
|
|
|
mutex_lock(&epc->lock);
|
|
ret = epc->ops->set_bar(epc, func_no, epf_bar);
|
|
mutex_unlock(&epc->lock);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_epc_set_bar);
|
|
|
|
/**
|
|
* pci_epc_write_header() - write standard configuration header
|
|
* @epc: the EPC device to which the configuration header should be written
|
|
* @func_no: the endpoint function number in the EPC device
|
|
* @header: standard configuration header fields
|
|
*
|
|
* Invoke to write the configuration header to the endpoint controller. Every
|
|
* endpoint controller will have a dedicated location to which the standard
|
|
* configuration header would be written. The callback function should write
|
|
* the header fields to this dedicated location.
|
|
*/
|
|
int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
|
|
struct pci_epf_header *header)
|
|
{
|
|
int ret;
|
|
|
|
if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
|
|
return -EINVAL;
|
|
|
|
if (!epc->ops->write_header)
|
|
return 0;
|
|
|
|
mutex_lock(&epc->lock);
|
|
ret = epc->ops->write_header(epc, func_no, header);
|
|
mutex_unlock(&epc->lock);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_epc_write_header);
|
|
|
|
/**
|
|
* pci_epc_add_epf() - bind PCI endpoint function to an endpoint controller
|
|
* @epc: the EPC device to which the endpoint function should be added
|
|
* @epf: the endpoint function to be added
|
|
* @type: Identifies if the EPC is connected to the primary or secondary
|
|
* interface of EPF
|
|
*
|
|
* A PCI endpoint device can have one or more functions. In the case of PCIe,
|
|
* the specification allows up to 8 PCIe endpoint functions. Invoke
|
|
* pci_epc_add_epf() to add a PCI endpoint function to an endpoint controller.
|
|
*/
|
|
int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf,
|
|
enum pci_epc_interface_type type)
|
|
{
|
|
struct list_head *list;
|
|
u32 func_no;
|
|
int ret = 0;
|
|
|
|
if (IS_ERR_OR_NULL(epc))
|
|
return -EINVAL;
|
|
|
|
if (type == PRIMARY_INTERFACE && epf->epc)
|
|
return -EBUSY;
|
|
|
|
if (type == SECONDARY_INTERFACE && epf->sec_epc)
|
|
return -EBUSY;
|
|
|
|
mutex_lock(&epc->lock);
|
|
func_no = find_first_zero_bit(&epc->function_num_map,
|
|
BITS_PER_LONG);
|
|
if (func_no >= BITS_PER_LONG) {
|
|
ret = -EINVAL;
|
|
goto ret;
|
|
}
|
|
|
|
if (func_no > epc->max_functions - 1) {
|
|
dev_err(&epc->dev, "Exceeding max supported Function Number\n");
|
|
ret = -EINVAL;
|
|
goto ret;
|
|
}
|
|
|
|
set_bit(func_no, &epc->function_num_map);
|
|
if (type == PRIMARY_INTERFACE) {
|
|
epf->func_no = func_no;
|
|
epf->epc = epc;
|
|
list = &epf->list;
|
|
} else {
|
|
epf->sec_epc_func_no = func_no;
|
|
epf->sec_epc = epc;
|
|
list = &epf->sec_epc_list;
|
|
}
|
|
|
|
list_add_tail(list, &epc->pci_epf);
|
|
ret:
|
|
mutex_unlock(&epc->lock);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_epc_add_epf);
|
|
|
|
/**
|
|
* pci_epc_remove_epf() - remove PCI endpoint function from endpoint controller
|
|
* @epc: the EPC device from which the endpoint function should be removed
|
|
* @epf: the endpoint function to be removed
|
|
*
|
|
* Invoke to remove PCI endpoint function from the endpoint controller.
|
|
*/
|
|
void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf,
|
|
enum pci_epc_interface_type type)
|
|
{
|
|
struct list_head *list;
|
|
u32 func_no = 0;
|
|
|
|
if (!epc || IS_ERR(epc) || !epf)
|
|
return;
|
|
|
|
if (type == PRIMARY_INTERFACE) {
|
|
func_no = epf->func_no;
|
|
list = &epf->list;
|
|
} else {
|
|
func_no = epf->sec_epc_func_no;
|
|
list = &epf->sec_epc_list;
|
|
}
|
|
|
|
mutex_lock(&epc->lock);
|
|
clear_bit(func_no, &epc->function_num_map);
|
|
list_del(list);
|
|
epf->epc = NULL;
|
|
mutex_unlock(&epc->lock);
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_epc_remove_epf);
|
|
|
|
/**
|
|
* pci_epc_linkup() - Notify the EPF device that EPC device has established a
|
|
* connection with the Root Complex.
|
|
* @epc: the EPC device which has established link with the host
|
|
*
|
|
* Invoke to Notify the EPF device that the EPC device has established a
|
|
* connection with the Root Complex.
|
|
*/
|
|
void pci_epc_linkup(struct pci_epc *epc)
|
|
{
|
|
if (!epc || IS_ERR(epc))
|
|
return;
|
|
|
|
atomic_notifier_call_chain(&epc->notifier, LINK_UP, NULL);
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_epc_linkup);
|
|
|
|
/**
|
|
* pci_epc_init_notify() - Notify the EPF device that EPC device's core
|
|
* initialization is completed.
|
|
* @epc: the EPC device whose core initialization is completeds
|
|
*
|
|
* Invoke to Notify the EPF device that the EPC device's initialization
|
|
* is completed.
|
|
*/
|
|
void pci_epc_init_notify(struct pci_epc *epc)
|
|
{
|
|
if (!epc || IS_ERR(epc))
|
|
return;
|
|
|
|
atomic_notifier_call_chain(&epc->notifier, CORE_INIT, NULL);
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_epc_init_notify);
|
|
|
|
/**
|
|
* pci_epc_destroy() - destroy the EPC device
|
|
* @epc: the EPC device that has to be destroyed
|
|
*
|
|
* Invoke to destroy the PCI EPC device
|
|
*/
|
|
void pci_epc_destroy(struct pci_epc *epc)
|
|
{
|
|
pci_ep_cfs_remove_epc_group(epc->group);
|
|
device_unregister(&epc->dev);
|
|
kfree(epc);
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_epc_destroy);
|
|
|
|
/**
|
|
* devm_pci_epc_destroy() - destroy the EPC device
|
|
* @dev: device that wants to destroy the EPC
|
|
* @epc: the EPC device that has to be destroyed
|
|
*
|
|
* Invoke to destroy the devres associated with this
|
|
* pci_epc and destroy the EPC device.
|
|
*/
|
|
void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc)
|
|
{
|
|
int r;
|
|
|
|
r = devres_destroy(dev, devm_pci_epc_release, devm_pci_epc_match,
|
|
epc);
|
|
dev_WARN_ONCE(dev, r, "couldn't find PCI EPC resource\n");
|
|
}
|
|
EXPORT_SYMBOL_GPL(devm_pci_epc_destroy);
|
|
|
|
/**
|
|
* __pci_epc_create() - create a new endpoint controller (EPC) device
|
|
* @dev: device that is creating the new EPC
|
|
* @ops: function pointers for performing EPC operations
|
|
* @owner: the owner of the module that creates the EPC device
|
|
*
|
|
* Invoke to create a new EPC device and add it to pci_epc class.
|
|
*/
|
|
struct pci_epc *
|
|
__pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
|
|
struct module *owner)
|
|
{
|
|
int ret;
|
|
struct pci_epc *epc;
|
|
|
|
if (WARN_ON(!dev)) {
|
|
ret = -EINVAL;
|
|
goto err_ret;
|
|
}
|
|
|
|
epc = kzalloc(sizeof(*epc), GFP_KERNEL);
|
|
if (!epc) {
|
|
ret = -ENOMEM;
|
|
goto err_ret;
|
|
}
|
|
|
|
mutex_init(&epc->lock);
|
|
INIT_LIST_HEAD(&epc->pci_epf);
|
|
ATOMIC_INIT_NOTIFIER_HEAD(&epc->notifier);
|
|
|
|
device_initialize(&epc->dev);
|
|
epc->dev.class = pci_epc_class;
|
|
epc->dev.parent = dev;
|
|
epc->ops = ops;
|
|
|
|
ret = dev_set_name(&epc->dev, "%s", dev_name(dev));
|
|
if (ret)
|
|
goto put_dev;
|
|
|
|
ret = device_add(&epc->dev);
|
|
if (ret)
|
|
goto put_dev;
|
|
|
|
epc->group = pci_ep_cfs_add_epc_group(dev_name(dev));
|
|
|
|
return epc;
|
|
|
|
put_dev:
|
|
put_device(&epc->dev);
|
|
kfree(epc);
|
|
|
|
err_ret:
|
|
return ERR_PTR(ret);
|
|
}
|
|
EXPORT_SYMBOL_GPL(__pci_epc_create);
|
|
|
|
/**
|
|
* __devm_pci_epc_create() - create a new endpoint controller (EPC) device
|
|
* @dev: device that is creating the new EPC
|
|
* @ops: function pointers for performing EPC operations
|
|
* @owner: the owner of the module that creates the EPC device
|
|
*
|
|
* Invoke to create a new EPC device and add it to pci_epc class.
|
|
* While at that, it also associates the device with the pci_epc using devres.
|
|
* On driver detach, release function is invoked on the devres data,
|
|
* then, devres data is freed.
|
|
*/
|
|
struct pci_epc *
|
|
__devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
|
|
struct module *owner)
|
|
{
|
|
struct pci_epc **ptr, *epc;
|
|
|
|
ptr = devres_alloc(devm_pci_epc_release, sizeof(*ptr), GFP_KERNEL);
|
|
if (!ptr)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
epc = __pci_epc_create(dev, ops, owner);
|
|
if (!IS_ERR(epc)) {
|
|
*ptr = epc;
|
|
devres_add(dev, ptr);
|
|
} else {
|
|
devres_free(ptr);
|
|
}
|
|
|
|
return epc;
|
|
}
|
|
EXPORT_SYMBOL_GPL(__devm_pci_epc_create);
|
|
|
|
static int __init pci_epc_init(void)
|
|
{
|
|
pci_epc_class = class_create(THIS_MODULE, "pci_epc");
|
|
if (IS_ERR(pci_epc_class)) {
|
|
pr_err("failed to create pci epc class --> %ld\n",
|
|
PTR_ERR(pci_epc_class));
|
|
return PTR_ERR(pci_epc_class);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
module_init(pci_epc_init);
|
|
|
|
static void __exit pci_epc_exit(void)
|
|
{
|
|
class_destroy(pci_epc_class);
|
|
}
|
|
module_exit(pci_epc_exit);
|
|
|
|
MODULE_DESCRIPTION("PCI EPC Library");
|
|
MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
|
|
MODULE_LICENSE("GPL v2");
|