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- If flash controller is halted unconditionally, this results in
illegal write access to flash controller register domain. Since
flash controller registers are only accessible once s_clk is started
- added logic to check for WGN status and halt flash controller only
if it is already running.
- Added check to wait for flash controller halt to be completed before
proceeding with s_clk/l_clk initializations.
- Removed unnecessary reset logic for PMM 1T memory and moved memory
initialization after flash access enable.
- Disable Brocade-1860 asic MBOX interrupt before PLL initialization.
- Remove reset enable for S_CLK/L_CLK after both PLL initializations
are complete.
Signed-off-by: Krishna Gudipati <kgudipat@brocade.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
10a0737924