f23b22599f
Add some basic documentation (zh_CN version) for LoongArch. LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit version (LA32S) and a 64-bit version (LA64). Reviewed-by: Alex Shi <alexs@kernel.org> Reviewed-by: Yanteng Si <siyanteng@loongson.cn> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Co-developed-by: WANG Xuerui <git@xen0n.name> Signed-off-by: WANG Xuerui <git@xen0n.name> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
27 lines
398 B
ReStructuredText
27 lines
398 B
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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.. include:: ../disclaimer-zh_CN.rst
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:Original: Documentation/loongarch/index.rst
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:Translator: Huacai Chen <chenhuacai@loongson.cn>
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=================
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LoongArch体系结构
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=================
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.. toctree::
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:maxdepth: 2
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:numbered:
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introduction
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irq-chip-model
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features
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.. only:: subproject and html
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Indices
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=======
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* :ref:`genindex`
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