84e85359f4
The Devicetree bindings document does not have to say in the title that
it is a "binding", but instead just describe the hardware.
Drop trailing "bindings" in various forms (also with trailing full
stop):
find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
-not -name 'trivial-devices.yaml' \
-exec sed -i -e 's/^title: \(.*\) [bB]indings\?\.\?$/title: \1/' {} \;
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Matti Vaittinen <mazziesaccount@gmail.com> # ROHM
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # input
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> # media
Acked-by: Sebastian Reichel <sre@kernel.org> # power
Acked-by: Viresh Kumar <viresh.kumar@linaro.org> # cpufreq
Link: https://lore.kernel.org/r/20221216163815.522628-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
75 lines
2.4 KiB
YAML
75 lines
2.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: NVIDIA Tegra CBB 2.0
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maintainers:
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- Sumit Gupta <sumitg@nvidia.com>
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description: |+
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The Control Backbone (CBB) is comprised of the physical path from an
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initiator to a target's register configuration space. CBB 2.0 consists
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of multiple sub-blocks connected to each other to create a topology.
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The Tegra234 SoC has different fabrics based on CBB 2.0 architecture
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which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and
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"CBB central fabric".
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In CBB 2.0, each initiator which can issue transactions connects to a
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Root Master Node (MN) before it connects to any other element of the
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fabric. Each Root MN contains a Error Monitor (EM) which detects and
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logs error. Interrupts from various EM blocks are collated by Error
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Notifier (EN) which is per fabric and presents a single interrupt from
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fabric to the SoC interrupt controller.
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The driver handles errors from CBB due to illegal register accesses
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and prints debug information about failed transaction on receiving
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the interrupt from EN. Debug information includes Error Code, Error
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Description, MasterID, Fabric, SlaveID, Address, Cache, Protection,
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Security Group etc on receiving error notification.
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If the Error Response Disable (ERD) is set/enabled for an initiator,
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then SError or Data abort exception error response is masked and an
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interrupt is used for reporting errors due to illegal accesses from
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that initiator. The value returned on read failures is '0xFFFFFFFF'
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for compatibility with PCIE.
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properties:
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$nodename:
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pattern: "^[a-z]+-fabric@[0-9a-f]+$"
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compatible:
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enum:
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- nvidia,tegra234-aon-fabric
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- nvidia,tegra234-bpmp-fabric
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- nvidia,tegra234-cbb-fabric
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- nvidia,tegra234-dce-fabric
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- nvidia,tegra234-rce-fabric
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- nvidia,tegra234-sce-fabric
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: secure interrupt from error notifier
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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cbb-fabric@1300000 {
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compatible = "nvidia,tegra234-cbb-fabric";
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reg = <0x13a00000 0x400000>;
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interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
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};
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