11fa5f8392
Document the newly added SM6125 GCC driver. Signed-off-by: Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20210605121040.282053-1-martin.botka@somainline.org Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
73 lines
1.5 KiB
YAML
73 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Qualcomm Global Clock & Reset Controller Binding for SM6125
|
|
|
|
maintainers:
|
|
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
|
|
|
description: |
|
|
Qualcomm global clock control module which supports the clocks, resets and
|
|
power domains on SM6125.
|
|
|
|
See also:
|
|
- dt-bindings/clock/qcom,gcc-sm6125.h
|
|
|
|
properties:
|
|
compatible:
|
|
const: qcom,gcc-sm6125
|
|
|
|
clocks:
|
|
items:
|
|
- description: Board XO source
|
|
- description: Sleep clock source
|
|
|
|
clock-names:
|
|
items:
|
|
- const: bi_tcxo
|
|
- const: sleep_clk
|
|
|
|
'#clock-cells':
|
|
const: 1
|
|
|
|
'#reset-cells':
|
|
const: 1
|
|
|
|
'#power-domain-cells':
|
|
const: 1
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
protected-clocks:
|
|
description:
|
|
Protected clock specifier list as per common clock binding.
|
|
|
|
required:
|
|
- compatible
|
|
- clocks
|
|
- clock-names
|
|
- reg
|
|
- '#clock-cells'
|
|
- '#reset-cells'
|
|
- '#power-domain-cells'
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/clock/qcom,rpmcc.h>
|
|
clock-controller@1400000 {
|
|
compatible = "qcom,gcc-sm6125";
|
|
reg = <0x01400000 0x1f0000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
clock-names = "bi_tcxo", "sleep_clk";
|
|
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
|
|
};
|
|
...
|