2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
217 lines
4.1 KiB
Plaintext
217 lines
4.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Keymile kmcoge4 Device Tree Source, based on the P2041RDB DTS
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*
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* (C) Copyright 2014
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* Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*/
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/include/ "p2041si-pre.dtsi"
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/ {
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model = "keymile,kmcoge4";
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compatible = "keymile,kmcoge4", "keymile,kmp204x";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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memory {
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device_type = "memory";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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bman_fbpr: bman-fbpr {
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size = <0 0x1000000>;
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alignment = <0 0x1000000>;
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};
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qman_fqd: qman-fqd {
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size = <0 0x400000>;
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alignment = <0 0x400000>;
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};
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qman_pfdr: qman-pfdr {
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size = <0 0x2000000>;
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alignment = <0 0x2000000>;
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};
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};
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dcsr: dcsr@f00000000 {
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ranges = <0x00000000 0xf 0x00000000 0x01008000>;
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};
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bportals: bman-portals@ff4000000 {
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ranges = <0x0 0xf 0xf4000000 0x200000>;
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};
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qportals: qman-portals@ff4200000 {
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ranges = <0x0 0xf 0xf4200000 0x200000>;
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};
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soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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spi@110000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,s25fl256s1", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <20000000>; /* input clock */
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};
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network_clock@1 {
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compatible = "zarlink,zl30343";
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reg = <1>;
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spi-max-frequency = <8000000>;
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};
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flash@2 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,m25p32", "jedec,spi-nor";
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reg = <2>;
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spi-max-frequency = <15000000>;
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};
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};
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sdhc@114000 {
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status = "disabled";
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};
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i2c@119000 {
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status = "disabled";
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};
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i2c@119100 {
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status = "disabled";
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};
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usb0: usb@210000 {
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status = "disabled";
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};
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usb1: usb@211000 {
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status = "disabled";
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};
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sata@220000 {
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status = "disabled";
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};
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sata@221000 {
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status = "disabled";
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};
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fman0: fman@400000 {
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enet0: ethernet@e0000 {
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phy-connection-type = "sgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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mdio0: mdio@e1120 {
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front_phy: ethernet-phy@11 {
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reg = <0x11>;
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};
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};
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enet1: ethernet@e2000 {
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phy-connection-type = "sgmii";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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enet2: ethernet@e4000 {
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status = "disabled";
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};
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enet3: ethernet@e6000 {
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status = "disabled";
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};
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enet4: ethernet@e8000 {
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phy-handle = <&front_phy>;
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phy-connection-type = "rgmii";
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};
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enet5: ethernet@f0000 {
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status = "disabled";
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};
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};
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};
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rio: rapidio@ffe0c0000 {
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status = "disabled";
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};
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lbc: localbus@ffe124000 {
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reg = <0xf 0xfe124000 0 0x1000>;
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ranges = <0 0 0xf 0xffa00000 0x00040000 /* LB 0 */
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1 0 0xf 0xfb000000 0x00010000 /* LB 1 */
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2 0 0xf 0xd0000000 0x10000000 /* LB 2 */
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3 0 0xf 0xe0000000 0x10000000>; /* LB 3 */
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nand@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,elbc-fcm-nand";
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reg = <0 0 0x40000>;
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};
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board-control@1,0 {
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compatible = "keymile,qriox";
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reg = <1 0 0x80>;
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};
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chassis-mgmt@3,0 {
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compatible = "keymile,bfticu";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <3 0 0x100>;
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interrupt-parent = <&mpic>;
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interrupts = <6 1 0 0>;
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};
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};
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pci0: pcie@ffe200000 {
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reg = <0xf 0xfe200000 0 0x1000>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
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0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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pci1: pcie@ffe201000 {
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status = "disabled";
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};
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pci2: pcie@ffe202000 {
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reg = <0xf 0xfe202000 0 0x1000>;
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ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
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0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0 0xe0000000
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0x02000000 0 0xe0000000
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0 0x20000000
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0x01000000 0 0x00000000
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0x01000000 0 0x00000000
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0 0x00010000>;
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};
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};
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};
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/include/ "p2041si-post.dtsi"
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