12b8567f6f
Add xcbc(aes) offloading support. Due to xcbc algorithm design and HW implementation in CAAM, driver must still have some bytes to send to the crypto engine when ahash_final() is called - such that HW correctly uses either K2 or K3 for the last block. Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com> Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
24 lines
825 B
C
24 lines
825 B
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
|
|
/*
|
|
* Shared descriptors for ahash algorithms
|
|
*
|
|
* Copyright 2017 NXP
|
|
*/
|
|
|
|
#ifndef _CAAMHASH_DESC_H_
|
|
#define _CAAMHASH_DESC_H_
|
|
|
|
/* length of descriptors text */
|
|
#define DESC_AHASH_BASE (3 * CAAM_CMD_SZ)
|
|
#define DESC_AHASH_UPDATE_LEN (6 * CAAM_CMD_SZ)
|
|
#define DESC_AHASH_UPDATE_FIRST_LEN (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
|
|
#define DESC_AHASH_FINAL_LEN (DESC_AHASH_BASE + 5 * CAAM_CMD_SZ)
|
|
#define DESC_AHASH_DIGEST_LEN (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
|
|
|
|
void cnstr_shdsc_ahash(u32 * const desc, struct alginfo *adata, u32 state,
|
|
int digestsize, int ctx_len, bool import_ctx, int era);
|
|
|
|
void cnstr_shdsc_axcbc(u32 * const desc, struct alginfo *adata, u32 state,
|
|
int digestsize, int ctx_len, dma_addr_t key_dma);
|
|
#endif /* _CAAMHASH_DESC_H_ */
|