12f9ce4a51
The current implementation always round down the duty and period values,
while it would be better to round them to the closest integer.
These changes are needed in preparation of atomic update support to
prevent a period/duty cycle drift when executing several times the
'pwm_get_state() / modify / pwm_apply_state()' sequence.
Say you have an expected period of 3.333 us and a clk rate of
112.666667 MHz -- the clock frequency doesn't divide evenly, so the
period (stashed in nanoseconds) shrinks when we convert to the register
value and back, as follows:
pwm_apply_state(): register = period * 112666667 / 1000000000;
pwm_get_state(): period = register * 1000000000 / 112666667;
or in other words:
period = period * 112666667 / 1000000000 * 1000000000 / 112666667;
which yields a sequence like:
3333 -> 3328
3328 -> 3319
3319 -> 3310
3310 -> 3301
3301 -> 3292
3292 -> ... (etc) ...
With this patch, we'd see instead:
period = div_round_closest(period * 112666667, 1000000000) *
1000000000 / 112666667;
which yields a stable sequence:
3333 -> 3337
3337 -> 3337
3337 -> ... (etc) ...
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
303 lines
7.1 KiB
C
303 lines
7.1 KiB
C
/*
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* PWM driver for Rockchip SoCs
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*
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* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
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* Copyright (C) 2014 ROCKCHIP, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/time.h>
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#define PWM_CTRL_TIMER_EN (1 << 0)
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#define PWM_CTRL_OUTPUT_EN (1 << 3)
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#define PWM_ENABLE (1 << 0)
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#define PWM_CONTINUOUS (1 << 1)
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#define PWM_DUTY_POSITIVE (1 << 3)
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#define PWM_DUTY_NEGATIVE (0 << 3)
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#define PWM_INACTIVE_NEGATIVE (0 << 4)
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#define PWM_INACTIVE_POSITIVE (1 << 4)
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#define PWM_OUTPUT_LEFT (0 << 5)
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#define PWM_LP_DISABLE (0 << 8)
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struct rockchip_pwm_chip {
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struct pwm_chip chip;
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struct clk *clk;
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const struct rockchip_pwm_data *data;
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void __iomem *base;
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};
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struct rockchip_pwm_regs {
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unsigned long duty;
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unsigned long period;
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unsigned long cntr;
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unsigned long ctrl;
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};
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struct rockchip_pwm_data {
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struct rockchip_pwm_regs regs;
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unsigned int prescaler;
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const struct pwm_ops *ops;
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void (*set_enable)(struct pwm_chip *chip,
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struct pwm_device *pwm, bool enable);
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};
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static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
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{
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return container_of(c, struct rockchip_pwm_chip, chip);
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}
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static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip,
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struct pwm_device *pwm, bool enable)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
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u32 val;
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val = readl_relaxed(pc->base + pc->data->regs.ctrl);
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if (enable)
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val |= enable_conf;
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else
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val &= ~enable_conf;
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writel_relaxed(val, pc->base + pc->data->regs.ctrl);
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}
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static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip,
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struct pwm_device *pwm, bool enable)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
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PWM_CONTINUOUS;
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u32 val;
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if (pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED)
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enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
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else
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enable_conf |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
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val = readl_relaxed(pc->base + pc->data->regs.ctrl);
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if (enable)
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val |= enable_conf;
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else
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val &= ~enable_conf;
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writel_relaxed(val, pc->base + pc->data->regs.ctrl);
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}
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static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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unsigned long period, duty;
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u64 clk_rate, div;
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int ret;
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clk_rate = clk_get_rate(pc->clk);
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/*
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* Since period and duty cycle registers have a width of 32
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* bits, every possible input period can be obtained using the
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* default prescaler value for all practical clock rate values.
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*/
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div = clk_rate * period_ns;
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period = DIV_ROUND_CLOSEST_ULL(div,
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pc->data->prescaler * NSEC_PER_SEC);
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div = clk_rate * duty_ns;
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duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
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ret = clk_enable(pc->clk);
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if (ret)
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return ret;
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writel(period, pc->base + pc->data->regs.period);
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writel(duty, pc->base + pc->data->regs.duty);
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writel(0, pc->base + pc->data->regs.cntr);
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clk_disable(pc->clk);
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return 0;
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}
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static int rockchip_pwm_set_polarity(struct pwm_chip *chip,
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struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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/*
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* No action needed here because pwm->polarity will be set by the core
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* and the core will only change polarity when the PWM is not enabled.
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* We'll handle things in set_enable().
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*/
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return 0;
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}
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static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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int ret;
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ret = clk_enable(pc->clk);
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if (ret)
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return ret;
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pc->data->set_enable(chip, pwm, true);
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return 0;
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}
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static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
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pc->data->set_enable(chip, pwm, false);
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clk_disable(pc->clk);
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}
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static const struct pwm_ops rockchip_pwm_ops_v1 = {
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.config = rockchip_pwm_config,
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.enable = rockchip_pwm_enable,
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.disable = rockchip_pwm_disable,
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.owner = THIS_MODULE,
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};
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static const struct pwm_ops rockchip_pwm_ops_v2 = {
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.config = rockchip_pwm_config,
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.set_polarity = rockchip_pwm_set_polarity,
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.enable = rockchip_pwm_enable,
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.disable = rockchip_pwm_disable,
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.owner = THIS_MODULE,
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};
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static const struct rockchip_pwm_data pwm_data_v1 = {
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.regs = {
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.duty = 0x04,
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.period = 0x08,
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.cntr = 0x00,
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.ctrl = 0x0c,
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},
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.prescaler = 2,
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.ops = &rockchip_pwm_ops_v1,
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.set_enable = rockchip_pwm_set_enable_v1,
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};
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static const struct rockchip_pwm_data pwm_data_v2 = {
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.regs = {
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.duty = 0x08,
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.period = 0x04,
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.cntr = 0x00,
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.ctrl = 0x0c,
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},
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.prescaler = 1,
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.ops = &rockchip_pwm_ops_v2,
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.set_enable = rockchip_pwm_set_enable_v2,
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};
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static const struct rockchip_pwm_data pwm_data_vop = {
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.regs = {
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.duty = 0x08,
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.period = 0x04,
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.cntr = 0x0c,
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.ctrl = 0x00,
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},
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.prescaler = 1,
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.ops = &rockchip_pwm_ops_v2,
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.set_enable = rockchip_pwm_set_enable_v2,
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};
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static const struct of_device_id rockchip_pwm_dt_ids[] = {
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{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
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{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
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{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
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static int rockchip_pwm_probe(struct platform_device *pdev)
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{
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const struct of_device_id *id;
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struct rockchip_pwm_chip *pc;
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struct resource *r;
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int ret;
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id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
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if (!id)
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return -EINVAL;
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pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
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if (!pc)
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return -ENOMEM;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pc->base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(pc->base))
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return PTR_ERR(pc->base);
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pc->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(pc->clk))
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return PTR_ERR(pc->clk);
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ret = clk_prepare(pc->clk);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, pc);
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pc->data = id->data;
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pc->chip.dev = &pdev->dev;
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pc->chip.ops = pc->data->ops;
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pc->chip.base = -1;
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pc->chip.npwm = 1;
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if (pc->data->ops->set_polarity) {
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pc->chip.of_xlate = of_pwm_xlate_with_flags;
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pc->chip.of_pwm_n_cells = 3;
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}
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ret = pwmchip_add(&pc->chip);
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if (ret < 0) {
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clk_unprepare(pc->clk);
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dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
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}
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return ret;
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}
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static int rockchip_pwm_remove(struct platform_device *pdev)
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{
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struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
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clk_unprepare(pc->clk);
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return pwmchip_remove(&pc->chip);
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}
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static struct platform_driver rockchip_pwm_driver = {
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.driver = {
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.name = "rockchip-pwm",
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.of_match_table = rockchip_pwm_dt_ids,
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},
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.probe = rockchip_pwm_probe,
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.remove = rockchip_pwm_remove,
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};
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module_platform_driver(rockchip_pwm_driver);
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MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
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MODULE_DESCRIPTION("Rockchip SoC PWM driver");
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MODULE_LICENSE("GPL v2");
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