59a582ad13
Andrew Jones <ajones@ventanamicro.com> says: When a DT puts zicbom in the isa string, but does not provide a block size, ALT_CMO_OP() will attempt to do cache operations on address zero since the start address will be ANDed with zero. We can't simply BUG() in riscv_init_cbom_blocksize() when we fail to find a block size because the failure will happen before logging works, leaving users to scratch their heads as to why the boot hung. Instead, ensure Zicbom is disabled and output an error which will hopefully alert people that the DT needs to be fixed. While at it, add a check that the block size is a power-of-2 too. * b4-shazam-merge: RISC-V: Ensure Zicbom has a valid block size RISC-V: Introduce riscv_isa_extension_check RISC-V: Improve use of isa2hwcap[] Link: https://lore.kernel.org/r/20221129143447.49714-1-ajones@ventanamicro.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
134 lines
3.3 KiB
C
134 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2017 SiFive
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*/
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#include <linux/of.h>
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#include <asm/cacheflush.h>
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#ifdef CONFIG_SMP
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#include <asm/sbi.h>
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static void ipi_remote_fence_i(void *info)
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{
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return local_flush_icache_all();
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}
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void flush_icache_all(void)
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{
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local_flush_icache_all();
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if (IS_ENABLED(CONFIG_RISCV_SBI))
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sbi_remote_fence_i(NULL);
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else
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on_each_cpu(ipi_remote_fence_i, NULL, 1);
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}
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EXPORT_SYMBOL(flush_icache_all);
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/*
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* Performs an icache flush for the given MM context. RISC-V has no direct
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* mechanism for instruction cache shoot downs, so instead we send an IPI that
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* informs the remote harts they need to flush their local instruction caches.
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* To avoid pathologically slow behavior in a common case (a bunch of
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* single-hart processes on a many-hart machine, ie 'make -j') we avoid the
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* IPIs for harts that are not currently executing a MM context and instead
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* schedule a deferred local instruction cache flush to be performed before
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* execution resumes on each hart.
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*/
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void flush_icache_mm(struct mm_struct *mm, bool local)
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{
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unsigned int cpu;
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cpumask_t others, *mask;
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preempt_disable();
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/* Mark every hart's icache as needing a flush for this MM. */
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mask = &mm->context.icache_stale_mask;
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cpumask_setall(mask);
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/* Flush this hart's I$ now, and mark it as flushed. */
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cpu = smp_processor_id();
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cpumask_clear_cpu(cpu, mask);
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local_flush_icache_all();
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/*
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* Flush the I$ of other harts concurrently executing, and mark them as
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* flushed.
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*/
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cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
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local |= cpumask_empty(&others);
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if (mm == current->active_mm && local) {
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/*
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* It's assumed that at least one strongly ordered operation is
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* performed on this hart between setting a hart's cpumask bit
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* and scheduling this MM context on that hart. Sending an SBI
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* remote message will do this, but in the case where no
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* messages are sent we still need to order this hart's writes
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* with flush_icache_deferred().
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*/
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smp_mb();
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} else if (IS_ENABLED(CONFIG_RISCV_SBI)) {
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sbi_remote_fence_i(&others);
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} else {
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on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1);
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}
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preempt_enable();
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}
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#endif /* CONFIG_SMP */
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#ifdef CONFIG_MMU
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void flush_icache_pte(pte_t pte)
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{
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struct page *page = pte_page(pte);
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/*
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* HugeTLB pages are always fully mapped, so only setting head page's
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* PG_dcache_clean flag is enough.
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*/
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if (PageHuge(page))
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page = compound_head(page);
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if (!test_and_set_bit(PG_dcache_clean, &page->flags))
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flush_icache_all();
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}
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#endif /* CONFIG_MMU */
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unsigned int riscv_cbom_block_size;
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EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
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void riscv_init_cbom_blocksize(void)
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{
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struct device_node *node;
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unsigned long cbom_hartid;
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u32 val, probed_block_size;
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int ret;
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probed_block_size = 0;
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for_each_of_cpu_node(node) {
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unsigned long hartid;
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ret = riscv_of_processor_hartid(node, &hartid);
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if (ret)
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continue;
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/* set block-size for cbom extension if available */
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ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
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if (ret)
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continue;
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if (!probed_block_size) {
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probed_block_size = val;
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cbom_hartid = hartid;
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} else {
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if (probed_block_size != val)
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pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
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cbom_hartid, hartid);
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}
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}
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if (probed_block_size)
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riscv_cbom_block_size = probed_block_size;
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}
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