Bill Huang 139fd30943 clk: tegra: Add Super Gen5 Logic
Super clock divider control and clock source mux of Tegra210 has changed
a little against prior SoCs, this patch adds Gen5 logic to address those
differences.

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-17 13:37:55 +01:00
..
2015-11-13 20:35:54 -08:00
2015-11-10 15:00:03 -08:00
2015-12-17 13:37:55 +01:00
2015-11-10 10:05:17 -08:00
2015-11-06 14:22:15 -08:00
2015-11-11 10:21:34 -08:00
2015-11-10 15:00:03 -08:00
2015-11-06 14:22:15 -08:00
2015-11-10 15:00:03 -08:00
2015-11-05 13:15:12 -08:00
2015-11-13 20:35:54 -08:00
2015-11-05 13:15:12 -08:00
2015-10-29 09:02:16 +09:00
2015-11-10 15:00:03 -08:00
2015-11-12 07:06:18 -05:00
2015-11-06 14:22:15 -08:00
2015-11-05 13:15:12 -08:00
2015-11-08 16:24:43 -05:00
2015-11-10 16:32:11 -08:00
2015-11-04 14:47:13 -08:00
2015-11-13 21:53:18 -08:00
2015-11-06 10:23:50 -08:00
2015-11-11 09:16:10 -08:00
2015-11-05 13:15:12 -08:00
2015-11-10 10:01:21 -08:00
2015-11-13 20:35:54 -08:00
2015-11-10 15:00:03 -08:00
2015-11-04 22:15:15 -08:00
2015-11-13 20:35:54 -08:00
2015-11-06 14:22:15 -08:00
2015-11-13 20:35:54 -08:00
2015-11-04 21:50:37 -08:00
2015-11-13 17:05:32 -08:00
2015-11-10 10:00:09 -08:00
2015-11-04 22:15:15 -08:00
2015-11-04 22:15:15 -08:00
2015-11-04 22:15:15 -08:00