142439b052
Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented, so removing defines for it won't change anything. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
133 lines
4.0 KiB
C
133 lines
4.0 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2002, 2004, 2007 by Ralf Baechle
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* Copyright (C) 2007 Maciej W. Rozycki
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*/
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#ifndef _ASM_WAR_H
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#define _ASM_WAR_H
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#include <war.h>
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/*
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* Work around certain R4000 CPU errata (as implemented by GCC):
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*
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* - A double-word or a variable shift may give an incorrect result
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* if executed immediately after starting an integer division:
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* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
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* erratum #28
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* "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
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* #19
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*
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* - A double-word or a variable shift may give an incorrect result
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* if executed while an integer multiplication is in progress:
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* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
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* errata #16 & #28
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*
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* - An integer division may give an incorrect result if started in
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* a delay slot of a taken branch or a jump:
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* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
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* erratum #52
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*/
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#ifdef CONFIG_CPU_R4000_WORKAROUNDS
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#define R4000_WAR 1
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#else
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#define R4000_WAR 0
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#endif
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/*
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* Work around certain R4400 CPU errata (as implemented by GCC):
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*
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* - A double-word or a variable shift may give an incorrect result
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* if executed immediately after starting an integer division:
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* "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
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* "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
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*/
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#ifdef CONFIG_CPU_R4400_WORKAROUNDS
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#define R4400_WAR 1
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#else
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#define R4400_WAR 0
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#endif
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/*
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* Work around the "daddi" and "daddiu" CPU errata:
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*
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* - The `daddi' instruction fails to trap on overflow.
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* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
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* erratum #23
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*
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* - The `daddiu' instruction can produce an incorrect result.
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* "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
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* erratum #41
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* "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
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* #15
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* "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
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* "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
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*/
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#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
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#define DADDI_WAR 1
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#else
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#define DADDI_WAR 0
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#endif
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/*
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* Workaround for the Sibyte M3 errata the text of which can be found at
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*
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* http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
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*
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* This will enable the use of a special TLB refill handler which does a
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* consistency check on the information in c0_badvaddr and c0_entryhi and
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* will just return and take the exception again if the information was
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* found to be inconsistent.
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*/
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#ifndef BCM1250_M3_WAR
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#error Check setting of BCM1250_M3_WAR for your platform
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#endif
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/*
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* This is a DUART workaround related to glitches around register accesses
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*/
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#ifndef SIBYTE_1956_WAR
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#error Check setting of SIBYTE_1956_WAR for your platform
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#endif
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/*
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* From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
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* the line which this instruction itself exists, the following
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* operation is not guaranteed."
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*
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* Workaround: do two phase flushing for Index_Invalidate_I
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*/
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#ifndef TX49XX_ICACHE_INDEX_INV_WAR
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#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
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#endif
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/*
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* The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
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* opposes it being called that) where invalid instructions in the same
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* I-cache line worth of instructions being fetched may case spurious
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* exceptions.
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*/
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#ifndef ICACHE_REFILLS_WORKAROUND_WAR
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#error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform
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#endif
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/*
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* On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
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* may cause ll / sc and lld / scd sequences to execute non-atomically.
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*/
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#ifndef R10000_LLSC_WAR
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#error Check setting of R10000_LLSC_WAR for your platform
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#endif
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/*
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* 34K core erratum: "Problems Executing the TLBR Instruction"
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*/
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#ifndef MIPS34K_MISSED_ITLB_WAR
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#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
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#endif
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#endif /* _ASM_WAR_H */
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