a26c56ae67
Use the `marvell,reg-init` DT property to configure the LED[2]/INTn pin
of the Marvell 88E1514 ethernet PHY on Turris Omnia into interrupt mode.
Without this the pin is by default in LED[2] mode, and the Marvell PHY
driver configures LED[2] into "On - Link, Blink - Activity" mode.
This fixes the issue where the pca9538 GPIO/interrupt controller (which
can't mask interrupts in HW) received too many interrupts and after a
time started ignoring the interrupt with error message:
IRQ 71: nobody cared
There is a work in progress to have the Marvell PHY driver support
parsing PHY LED nodes from OF and registering the LEDs as Linux LED
class devices. Once this is done the PHY driver can also automatically
set the pin into INTn mode if it does not find LED[2] in OF.
Until then, though, we fix this via `marvell,reg-init` DT property.
Signed-off-by: Marek Behún <kabel@kernel.org>
Reported-by: Rui Salvaterra <rsalvaterra@gmail.com>
Fixes: 26ca8b52d6 ("ARM: dts: add support for Turris Omnia")
Cc: Uwe Kleine-König <uwe@kleine-koenig.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: <stable@vger.kernel.org>
Tested-by: Rui Salvaterra <rsalvaterra@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
525 lines
9.6 KiB
Plaintext
525 lines
9.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Device Tree file for the Turris Omnia
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*
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* Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
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* Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
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*
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* Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include "armada-385.dtsi"
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/ {
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model = "Turris Omnia";
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compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
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chosen {
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stdout-path = &uart0;
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x40000000>; /* 1024 MB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
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MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
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internal-regs {
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/* USB part of the PCIe2/USB 2.0 port */
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usb@58000 {
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status = "okay";
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};
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sata@a8000 {
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status = "okay";
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};
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sdhci@d8000 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdhci_pins>;
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status = "okay";
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bus-width = <8>;
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no-1-8-v;
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non-removable;
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};
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usb3@f0000 {
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status = "okay";
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};
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usb3@f8000 {
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status = "okay";
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};
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};
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pcie {
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status = "okay";
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@2,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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pcie@3,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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};
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};
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sfp: sfp {
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compatible = "sff,sfp";
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i2c-bus = <&sfp_i2c>;
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tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
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tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
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rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
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los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
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mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
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maximum-power-milliwatt = <3000>;
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/*
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* For now this has to be enabled at boot time by U-Boot when
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* a SFP module is present. Read more in the comment in the
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* eth2 node below.
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*/
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status = "disabled";
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};
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};
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&bm {
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status = "okay";
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};
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&bm_bppi {
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status = "okay";
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};
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/* Connected to 88E6176 switch, port 6 */
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ð0 {
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pinctrl-names = "default";
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pinctrl-0 = <&ge0_rgmii_pins>;
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status = "okay";
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phy-mode = "rgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <0>;
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bm,pool-short = <3>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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/* Connected to 88E6176 switch, port 5 */
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ð1 {
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pinctrl-names = "default";
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pinctrl-0 = <&ge1_rgmii_pins>;
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status = "okay";
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phy-mode = "rgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <1>;
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bm,pool-short = <3>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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/* WAN port */
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ð2 {
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/*
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* eth2 is connected via a multiplexor to both the SFP cage and to
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* ethernet-phy@1. The multiplexor switches the signal to SFP cage when
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* a SFP module is present, as determined by the mode-def0 GPIO.
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*
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* Until kernel supports this configuration properly, in case SFP module
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* is present, U-Boot has to enable the sfp node above, remove phy
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* handle and add managed = "in-band-status" property.
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*/
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&phy1>;
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phys = <&comphy5 2>;
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sfp = <&sfp>;
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buffer-manager = <&bm>;
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bm,pool-long = <2>;
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bm,pool-short = <3>;
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};
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&i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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i2cmux@70 {
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compatible = "nxp,pca9547";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* STM32F0 command interface at address 0x2a */
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led-controller@2b {
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compatible = "cznic,turris-omnia-leds";
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reg = <0x2b>;
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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* LEDs are controlled by MCU (STM32F0) at
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* address 0x2b.
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*
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* The driver does not support HW control mode
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* for the LEDs yet. Disable the LEDs for now.
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*
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* Also LED functions are not stable yet:
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* - there are 3 LEDs connected via MCU to PCIe
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* ports. One of these ports supports mSATA.
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* There is no mSATA nor PCIe function.
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* For now we use LED_FUNCTION_WLAN, since
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* in most cases users have wifi cards in
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* these slots
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* - there are 2 LEDs dedicated for user: A and
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* B. Again there is no such function defined.
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* For now we use LED_FUNCTION_INDICATOR
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*/
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status = "disabled";
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multi-led@0 {
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reg = <0x0>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_INDICATOR;
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function-enumerator = <2>;
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};
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multi-led@1 {
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reg = <0x1>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_INDICATOR;
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function-enumerator = <1>;
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};
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multi-led@2 {
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reg = <0x2>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_WLAN;
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function-enumerator = <3>;
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};
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multi-led@3 {
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reg = <0x3>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_WLAN;
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function-enumerator = <2>;
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};
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multi-led@4 {
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reg = <0x4>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_WLAN;
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function-enumerator = <1>;
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};
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multi-led@5 {
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reg = <0x5>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_WAN;
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};
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multi-led@6 {
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reg = <0x6>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <4>;
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};
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multi-led@7 {
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reg = <0x7>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <3>;
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};
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multi-led@8 {
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reg = <0x8>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <2>;
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};
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multi-led@9 {
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reg = <0x9>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <1>;
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};
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multi-led@a {
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reg = <0xa>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <0>;
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};
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multi-led@b {
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reg = <0xb>;
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color = <LED_COLOR_ID_RGB>;
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function = LED_FUNCTION_POWER;
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};
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};
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eeprom@54 {
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compatible = "atmel,24c64";
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reg = <0x54>;
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/* The EEPROM contains data for bootloader.
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* Contents:
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* struct omnia_eeprom {
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* u32 magic; (=0x0341a034 in LE)
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* u32 ramsize; (in GiB)
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* char regdomain[4];
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* u32 crc32;
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* };
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*/
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* routed to PCIe0/mSATA connector (CN7A) */
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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/* routed to PCIe1/USB2 connector (CN61A) */
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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/* routed to PCIe2 connector (CN62A) */
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};
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sfp_i2c: i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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/* routed to SFP+ */
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};
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i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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/* ATSHA204A at address 0x64 */
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};
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i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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/* exposed on pin header */
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};
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i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <7>;
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pcawan: gpio@71 {
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/*
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* GPIO expander for SFP+ signals and
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* and phy irq
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*/
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compatible = "nxp,pca9538";
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reg = <0x71>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcawan_pins>;
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interrupt-parent = <&gpio1>;
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interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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};
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&mdio {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_pins>;
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status = "okay";
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phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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marvell,reg-init = <3 18 0 0x4985>;
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/* irq is connected to &pcawan pin 7 */
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};
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/* Switch MV88E6176 at address 0x10 */
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switch@10 {
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pinctrl-names = "default";
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pinctrl-0 = <&swint_pins>;
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compatible = "marvell,mv88e6085";
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#address-cells = <1>;
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#size-cells = <0>;
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dsa,member = <0 0>;
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reg = <0x10>;
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interrupt-parent = <&gpio1>;
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interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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ports@0 {
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reg = <0>;
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label = "lan0";
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};
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ports@1 {
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reg = <1>;
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label = "lan1";
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};
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ports@2 {
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reg = <2>;
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label = "lan2";
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};
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ports@3 {
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reg = <3>;
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label = "lan3";
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};
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ports@4 {
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reg = <4>;
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label = "lan4";
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};
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ports@5 {
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reg = <5>;
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label = "cpu";
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ethernet = <ð1>;
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phy-mode = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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/* port 6 is connected to eth0 */
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};
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};
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};
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&pinctrl {
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pcawan_pins: pcawan-pins {
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marvell,pins = "mpp46";
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marvell,function = "gpio";
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};
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swint_pins: swint-pins {
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marvell,pins = "mpp45";
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marvell,function = "gpio";
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};
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spi0cs0_pins: spi0cs0-pins {
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marvell,pins = "mpp25";
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marvell,function = "spi0";
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};
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spi0cs1_pins: spi0cs1-pins {
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marvell,pins = "mpp26";
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marvell,function = "spi0";
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
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status = "okay";
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spi-nor@0 {
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compatible = "spansion,s25fl164k", "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <40000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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reg = <0x0 0x00100000>;
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label = "U-Boot";
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};
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partition@100000 {
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reg = <0x00100000 0x00700000>;
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label = "Rescue system";
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};
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};
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};
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/* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
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};
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&uart0 {
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/* Pin header CN10 */
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&uart1 {
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/* Pin header CN11 */
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "okay";
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};
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